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N.A.T. nat-mch Technical Reference

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NAT-MCH Clock-Module – Technical Reference Manual
NAT-MCH
Clock-Module
Technical Reference Manual V 1.4
CLK Module HW
Revision 2.1 and Revision 2.3

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  • Page 1 NAT-MCH Clock-Module – Technical Reference Manual NAT-MCH Clock-Module Technical Reference Manual V 1.4 CLK Module HW Revision 2.1 and Revision 2.3...
  • Page 2 NAT-MCH Clock-PCB – Technical Reference Manual The NAT-MCH has been designed by: N.A.T. GmbH Kamillenweg 22 D-53757 Sankt Augustin Phone: ++49/2241/3989-0 Fax: ++49/2241/3989-10 E-Mail: support@nateurope.com Internet: http://www.nateurope.com Version 1.4 © N.A.T. GmbH...
  • Page 3 NAT-MCH Clock-PCB – Technical Reference Manual Disclaimer The following documentation, compiled by N.A.T. GmbH (henceforth called N.A.T.), repre- sents the current status of the product’s development. The documentation is updated on a regular basis. Any changes which might ensue, including those necessitated by updated speci- fications, are considered in the latest version of this documentation.

  • Page 4: Table Of Contents

    Power supply..........................12 3.2.3 Automatic Power Up ........................12 INTRODUCTION ............................. 13 CLK MODULE BASICS .......................... 14 BLOCK DIAGRAM OF THE NAT-MCH CLK MODULE ..............15 BOARD FEATURES ..........................16 FUNCTIONAL BLOCKS......................... 18 3 PLL ..........................18 TRATUM ..........................19...
  • Page 5 List of Figures Figure 2: Block Diagram of the NAT-MCH CLK Module ............. 15 Figure 5: Location Diagram of the NAT-MCH CLK Module v2.1 (top-view)....... 21 Figure 6: Location diagram of the NAT-MCH CLK Module v2.1 (bottom-view)....21 Figure 9: Connectors of the NAT-MCH CLK Module (top view) .......... 23 Figure 10: Connectors of the NAT-MCH CLK Module (bottom view) ........
  • Page 6 NAT-MCH Clock-PCB – Technical Reference Manual List of Tables Table 1: List of used Abbreviations ..................8 Table 2: NAT-MCH CLK Module Features ................ 9 Table 3: MCH Connector CON1..................24 Table 4: Connector to Basic-PCB CON2................26 Table 5: Connector to Hub-PCB CON3................
  • Page 7 NAT-MCH Clock-PCB – Technical Reference Manual Table 42: PLL_CTR2 - Register Bits................... 46 Table 43: PLL_Outp Register ....................47 Table 44: PLL_Outp - Register Bits..................47 Table 45: RES_1 Register ....................48 Table 46: RES_2 Register ....................48 Table 47: RES_3 Register ....................

  • Page 8: Conventions

    NAT-MCH Clock-PCB – Technical Reference Manual Conventions If not otherwise specified, addresses and memory maps are written in hexadecimal notation, identified by 0x. Table 1: gives a list of the abbreviations used in this document: Table 1: List of used Abbreviations...

  • Page 9: Board Specification

    NAT-MCH Clock-PCB – Technical Reference Manual 1 Board Specification Table 2: NAT-MCH CLK Module Features Power Consumption 12 V / 0.5 A max. (only CLK Module) Environmental Temperature (operating): 0°C to +50°C with forced cooling Conditions Temperature (storage): -40°C to +85°C...

  • Page 10: Statement On Environmental Protection

    NAT-MCH Clock-PCB – Technical Reference Manual 2 Statement on Environmental Protection 2.1 Compliance to RoHS Directive Directive 2002/95/EC of the European Commission on the "Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment" (RoHS) predicts that all electrical and electronic equipment being put on the European market...

  • Page 11: Compliance To Ce Directive

    NAT-MCH Clock-PCB – Technical Reference Manual As N.A.T. products are solely sold to industrial customers, by special arrangement at time of purchase the customer agreed to take the responsibility for a WEEE compliant disposal of the used N.A.T. product. Moreover, all N.A.T. products are marked according to the directive with a crossed out bin to indicate that these products within the European Community must not be disposed with regular waste.

  • Page 12: Installation

    The power supply for the NAT-MCH CLK Module must meet the following specifica- tions: +12 V / 0.5 A max. (only CLK Module, in addition to other PCBs of the NAT-MCH). 3.2.3 Automatic Power Up Power ramping/monitoring and power up reset generation is done by the NAT-MCH...

  • Page 13: Introduction

    The features of the individual modules are described in more detail in the corresponding Technical Reference Manuals. A general arrangement of the different modules of a NAT-MCH is shown in Figure 1. Figure 1: Arrangement of different NAT-MCH Modules This Technical Reference Manual describes the Clock-PCB.

  • Page 14: Clk Module Basics

    • Telecom CLK signals can be distributed over all backplane clock connections and the front panel interface • CLK1 and CLK2 from all 12 AMCs, the update clocks from a second NAT-MCH, or a signal from the front panel interface can be used as reference for the PLL •...

  • Page 15: Block Diagram Of The Nat-Mch Clk Module

    NAT-MCH Clock-PCB – Technical Reference Manual 6 Block Diagram of the NAT-MCH CLK Module Figure 2: Block Diagram of the NAT-MCH CLK Module Version 1.4 © N.A.T. GmbH...

  • Page 16: Board Features

    The NAT-MCH CLK Module implements 2 update channels (update CLK1 and CLK3). These channels are full-duplex connections to a second NAT-MCH. They can only be used to send and receive telecom clock signals (not the PCI Express clock signal). Ext.-ref.-CLK: The NAT-MCH CLK Module supports an external reference clock in- or output, accessible via a face plate connector.
  • Page 17 NAT-MCH Clock-PCB – Technical Reference Manual • Interface to other NAT-MCH PCBs Basic PCB: - The Microprocessor on the CLK Module can be programmed by the ColdFire on the Basic-Module via a SPI interface. Normal communication between the Microprocessor and the ColdFire is done by IPMI messages via the I²C interface.

  • Page 18: Functional Blocks

    FPGA. By programming a FPGA register bit, any clock signal from any AMC (either CLK1 or CLK2) or from the other NAT-MCH (CLK1 or CLK3 update) can be connected to either of the two reference inputs of the PLL.

  • Page 19: Microprocessor

    NAT-MCH Clock-PCB – Technical Reference Manual 8.2 Microprocessor An Atmel 8-bit microprocessor resides on the CLK Module. With the help of this microprocessor, the ColdFire of the base board can configure all multiplexers implemented in the FPGA and enable the M-LVDS/HCSL transceivers for the connection to each AMCs.
  • Page 20 NAT-MCH Clock-PCB – Technical Reference Manual Figure 4: HCSL termination Because of this differences N.A.T. decided to offer two different assembly/ordering options SSCM (Spread Spectrum Clock M-LVDS) and SSCH (Spread Spectrum Clock HCSL). The SSCM option implements M-LVDS compliant Transmitter and termination for CLK3.

  • Page 21: Location Overview

    Hardware revision v2.1 implements the SSCM option and v2.3 the SSCH option Figure 5: Location Diagram of the NAT-MCH CLK Module v2.1 (top-view) Figure 6: Location diagram of the NAT-MCH CLK Module v2.1 (bottom-view) Version 1.4...
  • Page 22 NAT-MCH Clock-PCB – Technical Reference Manual Figure 7: Location Diagram of the NAT-MCH CLK Module v2.3 (top-view) Figure 8: Location Diagram of the NAT-MCH CLK Module v2.3 (bottom-view) Version 1.4 © N.A.T. GmbH...

  • Page 23: Connectors

    Figure 9: Connectors of the NAT-MCH CLK Module (top view) Figure 10: Connectors of the NAT-MCH CLK Module (bottom view) Please refer to the following tables for the pin assignment of the NAT-MCH CLK Module. Version 1.4 © N.A.T. GmbH...

  • Page 24: Mch Connector Con1

    NAT-MCH Clock-PCB – Technical Reference Manual 10.2 MCH Connector CON1 Table 3: MCH Connector CON1 Pin No. MCH-Signal MCH-Signal Pin No. RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD CLK3_Tx+ CLK3_Rx+ CLK3_Tx- CLK3_Rx- CLK1_Tx+ CLK1_Rx+ CLK1_Tx- CLK1_Rx- TxFB-1+ RxFB-1+ TxFB-1-...
  • Page 25 NAT-MCH Clock-PCB – Technical Reference Manual Pin No. MCH-Signal MCH-Signal Pin No. CLK3-3+ CLK3-9+ CLK3-3- CLK3-9- CLK3-4+ CLK3-10+ CLK3-4- CLK3-10- CLK3-5+ CLK3-11+ CLK3-5- CLK3-11- CLK3-6+ CLK3-12+ CLK3-6- CLK3-12- CLK1-1+ CLK2-1+ CLK1-1- CLK2-1- CLK1-2+ CLK2-2+ CLK1-2- CLK2-2- CLK1-3+ CLK2-3+ CLK1-3- CLK2-3-...

  • Page 26: Connector Con2: Interface To Basic-Pcb

    CLK1-11+ CLK2-11+ CLK1-11- CLK2-11- CLK1-12+ CLK2-12+ CLK1-12- CLK2-12- 10.3 Connector Con2: Interface to Basic-PCB Connector CON2 connects the NAT-MCH CLK Module with the Basic-PCB Table 4: Connector to Basic-PCB CON2 Pin No. Signal Signal Pin No. +12V +12V +12V +12V EXTREF_OUT_P +3.3V MP...

  • Page 27: Connector Con3: Interface To Hub-Pcb

    NAT-MCH Clock-PCB – Technical Reference Manual 10.4 Connector CON3: Interface to Hub-PCB Connector CON3 connects the CLK Module with the HUB-PCB. Table 5: Connector to Hub-PCB CON3 Pin No. Signal Signal Pin No. +12V +12V +12V +12V PCIeCLK_P +3.3V MP...

  • Page 28: Nat-Mch Clk Module Programming Notes

    NAT-MCH Clock-PCB – Technical Reference Manual NAT-MCH CLK Module Programming Notes 11.1 SPI Interface The SPI interface on the CLK Module is used only for maintenance purposes, e.g. updating the microcontroller firmware. 11.2 I²C Interface The I²C interface is the main communication interface between the microcontroller and the CPU of the Basic-Module.

  • Page 29: Board Identifier Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.1 Board Identifier Register The Board Identifier Register contains the Board ID that identifies the board as NAT-MCH CLK Module. Table 7: Board Identifier Register Board Identifier - Address 0x00 Default value 0xb4 Access...

  • Page 30: Fpga Revision Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.4 FPGA Revision Register The FPGA Revision Register contains the revision code of the Altera FPGA. Table 10: FPGA Revision Register FPGA Revision - Address 0x03 Default value # of running FPGA revision Access...

  • Page 31: Reference 0 Selection Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.5 Reference 0 Selection Register The value of the Reference 0 Selection Register decides which source is connected to REF0 of the PLL. Table 11: REF0_SEL Register Reference 0 Selection - Address 0x04 Default value 0x00...

  • Page 32: Reference 1 Selection Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.6 Reference 1 Selection Register The value of the Reference 1 Selection Register decides which source is connected to REF1 of the PLL. Table 13: REF1_SEL Register Reference 1 Selection - Address 0x05 Default value 0x00...

  • Page 33: Source Selection 1 Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.7 Source Selection 1 Register The value of the Source Selection 1 Register decides which output (of the PLL) is connected to the CLK1 Transceiver. Table 15: SRC_SEL1 Register Source Selection 1 - Address 0x06...

  • Page 34: Source Selection 2 Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.8 Source Selection 2 Register The value of the Source Selection 2 Register decides which output (of the PLL) is connected to the CLK2 Transceiver. Table 17: SRC_SEL2 Register Source Selection 2 – Address 0x07...

  • Page 35: Source Selection 3 Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.9 Source Selection 3 Register The value of the Source Selection 3 Register decides which output (of the PLL) is connected to the CLK3 Transceiver. Table 19: SRC_SEL3 Register Source Selection 3 – Address 0x08...

  • Page 36: Source Selection Clk1 Update Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.10 Source Selection CLK1 Update Register The value of the Source Selection CLK1 Update Register decides which output (of the PLL) is connected to the Update CLK1 Transceiver. Table 21: SRC_SEL_CLK1_UD Register Source Selection CLK1 Update – Address 0x09...

  • Page 37: Source Selection Clk3 Update Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.11 Source Selection CLK3 Update Register The value of the Source Selection CLK3 Update Register decides which output (of the PLL) is connected to the Update CLK3 Transceiver. Table 23: SRC_SEL_CLK3_UD Register Source Selection CLK3 Update – Address 0x0A...

  • Page 38: Transceiver Control 1 Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.12 Transceiver Control 1 Register The value of the Transceiver Control 1 Register controls the receive function of all M-LVDS transceiver and the transmit function of the Update M-LVDS transceiver. Table 25: TRANSC_CTL1 Register...

  • Page 39: Transceiver Control 2 Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.13 Transceiver Control 2 Register The value of the Transceiver Control 2 Register controls the transmit function of the M- LVDS transceiver for CLK1, AMC1-8. Table 27: TRANSC_CTL2 Register Transceiver Control 2 - Address 0x0C...

  • Page 40: Transceiver Control 3 Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.14 Transceiver Control 3 Register The value of the Transceiver Control 3 Register controls the transmit function of the M- LVDS transceiver for CLK1, AMC9-12. Table 29: TRANSC_CTL3 Register Transceiver Control 3 - Address 0x0D...

  • Page 41: Transceiver Control 4 Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.15 Transceiver Control 4 Register The value of the Transceiver Control 4 Register controls the transmit function of the M- LVDS transceiver for CLK2, AMC1-8. Table 31: TRANSC_CTL4 Register Transceiver Control 4 - Address 0x0E...

  • Page 42: Transceiver Control 5 Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.16 Transceiver Control 5 Register The value of the Transceiver Control 5 Register controls the transmit function of the M- LVDS transceiver for CLK2, AMC9-12. Table 33: TRANSC_CTL5 Register Transceiver Control 5 - Address 0x0F...

  • Page 43: Transceiver Control 6 Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.17 Transceiver Control 6 Register The value of the Transceiver Control 6 Register controls the transmit function of the M- LVDS transceiver for CLK3, AMC1-8. Table 35: TRANSC_CTL6 Register Transceiver Control 6 - Address 0x10...

  • Page 44: Transceiver Control 7 Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.18 Transceiver Control 7 Register The value of the Transceiver Control 7 Register controls the transmit function of the M- LVDS transceiver for CLK3, AMC9-12. Table 37: TRANSC_CTL7 Register Transceiver Control 7 - Address 0x11...

  • Page 45: Pll Control 1 Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.19 PLL Control 1 Register The PLL Control 1 Register manages together with the PLL_CTR2 Register the control inputs of the Zarlink PLL. Table 39: PLL_CTR1 Register PLL Control 1 - Address 0x12 Default value 0x00...

  • Page 46: Pll Control 2 Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.20 PLL Control 2 Register The PLL Control 2 Register manages together with the PLL_CTR1 Register the control inputs of the Zarlink PL L. Table 41: PLL_CTR2 Register PLL Control 2 - Address 0x13...

  • Page 47: Pll Output Signals Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.21 PLL Output Signals Register The PLL Output Signals Register shows the state of the PLL Output signals. Table 43: PLL_Outp Register PLL Output Signals - Address 0x14 Default value 0x00 Access HOLD- REF_FAIL...

  • Page 48: Reserved Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.22 Reserved Register The Reserved Register bytes are used for N.A.T. internal tests. Do not change the value of these Registers. Table 45: RES_1 Register Reserved 1 - Address 0x15 Default value 0x00 Access...

  • Page 49: Synchronized Clock Register

    NAT-MCH Clock-PCB – Technical Reference Manual Table 50: RES_6 Register Reserved 6 - Address 0x1A Default value 0x00 Access Func 11.3.23 Synchronized Clock Register The Synchronized Clock Register contains extended features to choose a source that can be distributed to all AMCs.

  • Page 50: Table 52: Sync_Clk - Register Bits

    NAT-MCH Clock-PCB – Technical Reference Manual Table 52: SYNC_CLK - Register Bits Name Function [4..0] SYNC_CLK_ The Sync Clock Selection bits control the SYNC_CLK multiplexer. The output of this multiplexer can be selected as a source for the CLK1-3. 0x01 – C19o 0x02 –...

  • Page 51: Led2 Control Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.24 LED2 Control Register The LED2 Control Register selects the LED2 function. Table 53: LED2_CTR Register LED2 Control - Address 0x1C Default value 0x00 Access Func LED2_CTR Table 54: LED2_CTR - Register Bits Name Function [2..0]...

  • Page 52: Holdover Function Control Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.25 Holdover Function Control Register The value of the Holdover Function Control Register controls the mode of the holdover function. Table 55: H_OVER_FUNKT_CTL Register Holdover Function Control - Address 0x2d Default value 0x00 Access...

  • Page 53: External Reference Output Control Register

    NAT-MCH Clock-PCB – Technical Reference Manual 11.3.26 External Reference Output Control Register The value of the External Reference Output Control Register enables and configures the external clock outpu. Table 57: EXT_REF_OUTP_CTL Register External ReferenceOutput Control - Address 0x2E Default value 0x00...
  • Page 54 NAT-MCH Clock-PCB – Technical Reference Manual 0x31 – CLK1 of AMC1 0x32 – CLK1 of AMC2 0x3C – CLK1 of AMC12 all other values result in no connection HIGH-AMPL Selects the Amplitude of the Output signal The CLK-Module output connects via two signals to the Base-Module, EXTREF_OUT_P and EXTREF_OUT_N (refer to Table 4: ).

  • Page 55: Known Bugs / Restrictions

    NAT-MCH Clock-PCB – Technical Reference Manual Known Bugs / Restrictions none Version 1.4 © N.A.T. GmbH...

  • Page 56: Appendix A: Reference Documentation

    NAT-MCH Clock-PCB – Technical Reference Manual Appendix A: Reference Documentation [1] Zarlink, ZL30105 T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTCA™ and H.110, 11/05 Version 1.4 © N.A.T. GmbH...

  • Page 57: Appendix B: Document's History

    NAT-MCH Clock-PCB – Technical Reference Manual Appendix B: Document’s History Revision Date Description Author 12.02.2008 initial revision 13.02.2008 Changed SYNC_CLK register description 05.06.2008 Added description of holdover function 12.08.2008 and external reference clock interface. 02.10.2008 Added description of HCSL and M-LVDS differences...

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