Vertex Standard VX-800 Service Manual page 17

Spurious Suppression
Generation of spurious products by the transmitter
is minimized by the fundamental carrier frequency
being equal to final transmitting frequency, modu-
lated directly in the transmit VCO. Additional har-
monic suppression is provided by a low-pass filter
consisting of L1004, L1005, and L1006 and C1013,
C1014, C1015, C1017, C1019, and C1020, resulting
in more than 60 dB of harmonic suppression prior
to delivery to the antenna.
PLL Frequency Synthesizer
The PLL frequency synthesizer consists of the VCO
Q1033 (2SC5226-4/5:RX) and Q1039 (2SC5226-4/
5:TX), VCO buffers Q1033 (2SC5226-4/5), Q1041
(2SC5226-4/5), and Q1030 (2SC52264/5), PLL sub-
system IC Q1054 (SA7025DK), and 21.6MHz refer-
ence crystal X1002.
The frequency stability is ±2.5 ppm within a tem-
perature range of –22°F to +140°F (–30°C to +60°C).
The output of the 21.6 MHz reference is applied to
pin 8 of the PLL IC.
While receiving, VCO Q1033 oscillates between
111.94 and 151.94 MHz according to the transceiver
version and the programmed receiving frequency,
for provision of the first local signal. In transmit, the
VCO generates a signal at 134 to 174 MHz.
The output of the VCO is amplified by the Q1041
and routed to pin 5 of the PLL IC. It also is amplified
by Q1030 and routed to the first local or Power Mod-
ule according to instructions from D1031.
Circuit Description
The PLL IC consists of a prescaler, fractional divider,
reference divider, phase comparator, charge pump.
This PLL IC is a fractional-N type synthesizer and
utilizes a 40 kHz, 50 kHz, or 60 kHz reference signal
which is the eighth harmonic of the channel step (5,
6.25 or 7.5kHz). The input signal from pin 5 and 8 of
the PLL IC is divided down to the 40/50/60 kHz ref-
erence, and compared at the phase comparator. The
pulsed output signal of the phase comparator is ap-
plied to the charge pump and transformed into a
DC signal in the loop filter. The DC signal is applied
to pin 1 of the VCO and locked to keep the VCO
frequency constant.
PLL data is sent from DTA (pin 100), CLK (pin 2)
and PSTB (pin 98) of the microprocessor Q1048. The
data are iapplied to the PLL IC when the channel is
changed or when transmission is changed to recep-
tion and vice versa. A PLL lock condition is always
monitored by pin 20 of Q1048. When the PLL is un-
locked, the "UL" line goes low.
Miscellaneous Circuits
Push-To-Talk Transmit Activation
The PTT switch on the microphone is connected to
pin 36 of microprocessor
Q1048, so that when the PTT switch is closed, pin 85
of Q1048 goes high. This signals the microprocessor
to activate the TX / RX controller Q1004 (UMG2N),
which then disables the receiver by disabling the 5
V supply bus at Q1011 (UN911F), which is fed to the
receiver front-end, FM IF subsystem IC Q1046, and
receiver VCO circuitry.
At the same time, Q1003 (XP1501) and Q1002
(CPH6102) activate the TX 5 V supply line to enable
the transmitter.
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