Kenwood DV-6050 Service Manual page 17

Pin No. Pin Name
47,49~52,54~56
HD0~HD15
58~60,62,63,65~67
69 AUDSTR
70 VSTR
71
73~76,78~81 STD7~STD0
83 IECOUT
84 DMIX
86 DACCK
87 LRCK
88 SRCK
90~92 ADOUT(0~2)
94 CLK121
95
96 CLK27
97 PLLVDD
98 CLK81
100 EXTCK
101 PLLAVDD
102 TCPOUT
103 PLLAVSS
106 PHCOPMO
107 APLLVDD
108 ACKIO
109 MODE121
110 DCTEST
111 APLLAVSS
112 APLLAVDD
113 VREFCR
114 IREFCR
115 COMPCR
116 VCROUT
117,127 AVDD
118 VREFC
119 IREFC
120 COMPC
121 VCOUT
122,132 AVSS
123 VREFCB
124 IREFCB
125 COMPCB
126 VCBOUT
128 VREFY
129 IREFY
130 COMPY
131 VYOUT
133,134 TESTSEL1,0
136 VCLK
137~140,142,143 REC(7~2)
REC1
144
XVSYNCO
REC0
145
XHSYNCO
147~150,152~155 VD0~VD7
CIRCUIT DESCRIPTION
I/O
I/O DVD microcomputer data bus 0~15.
I Valid signal of bit stream input data.
I Clock signal input for bit stream.
VRQ O Request of program stream.
I Bit stream parallel input 0~7.
O IEC958 format data output.
O Down mix signal output (CH7/CH8).
O Over sampling DAC clock output.
O LR clock output.
O Bit clock output.
O Audio data output (0~2).
I External clock (121.5MHz) input. (Unused)
CKIO I "L" : Fixed
I System clock input (27MHz).
- Supply voltage (+1.8V) of internal logic for main PLL.
- Connected to digital ground.
I Clock input for audio.
- Main PLL supply voltage (+3.3V).
0 Unused.
- Ground for main PLL.
O Audio PLL phase comparison output.
- Supply voltage (+1.8V) of internal logic for Audio PLL.
I "L" : Fixed
I Switching port for SDRAM clock frequency.
I DC test mode terminal.
- Ground for audio PLL.
- Supply voltage (+3.3V) for Audio PLL.
I DAC reference voltage input for CR signal.
I DAC bias current setting port for CR signal.
I Capacitance connection for DAC (CR signal) stabilization.
O CR signal output for DAC.
- Analog supply voltage (+3.3V) for DAC.
I DAC reference voltage input for C signal.
I DAC bias current setting port for C signal.
I Capacitance connection for DAC stabilization.
O C signal output for DAC.
- Analog ground for DAC.
I DAC reference voltage input for CB signal.
I DAC bias current setting port for CB signal.
I Capacitance connection for DAC (CB signal) stabilization.
O CB signal output for DAC.
I DAC reference voltage input for Y signal.
I DAC bias current setting port for Y signal.
I Capacitance connection for DAC (Y signal) stabilization.
O Y signal output for DAC.
I Test mode terminal.
O Clock output for digital video data output.
I/O REC656 input (7~2).
I/O REC656 input 1. Vertical synchronizing signal input/output.
I/O REC656 input 0. Horizontal synchronizing signal input/output.
O Digital video data output (0~7).
DV-6050
Pin Description
L : Fixed
17