Clevo W24ACZ Service Manual page 62

Processor 7/7
CFG Straps for Processor
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2 1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
CFG2
R111 *1K_04
Display Port Presence Strap
1:(Default) Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG4 R110 *1K_04
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG[6:5] 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG5 R99 *1K_04
CFG6 R92 *1K_04
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB de assertion
CFG7
0: PEG Wait for BIOS for training
CFG7
R93 *1K_04
Ivy/Sandy Bridge Processor 7/7
( RESERVED )
U 34E
F48
VCC_DIE_SENSE
CFG0 B50
C FG[0]
C51
C FG[1]
CFG2 B54 A4
C FG[2] DC_TEST_A4
D53 C 4
C FG[3] D C_TEST_C4
CFG4 A51 D 3
C FG[4] D C_TEST_D3
C53 D 1
CFG5
C FG[5] D C_TEST_D1
CFG6 C55 A58
C FG[6] DC_TEST_A58
H49 A59
CFG7
C FG[7] DC_TEST_A59
A55 C 59
H51 C FG[8] D C_TEST_C59 A61
C FG[9] DC_TEST_A61
K49 C 61
C FG[10] D C_TEST_C61
K53 D 61
C FG[11] D C_TEST_D61
F53 BD61
C FG[12] DC_TEST_BD61
G53 BE61
C FG[13] D C_TEST_BE61
L51 BE59
C FG[14] D C_TEST_BE59
F51 BG61
C FG[15] DC_TEST_BG61
D52 BG59
C FG[16] DC_TEST_BG59
L53 BG58
C FG[17] DC_TEST_BG58
BG4
DC_TEST_BG4
BG3
DC_TEST_BG3 BE3
D C_TEST_BE3
BG1
DC_TEST_BG1
H_CPU_RSVD1 H45 BE1
VAXG_VAL_SENSE D C_TEST_BE1
K45 BD1
H_CPU_RSVD2
VSSAXG_VAL_SEN SE DC_TEST_BD1
H_CPU_RSVD3 H43
VCC_VAL_SENSE
K43
H_CPU_RSVD4
VSS_VAL_SENSE
BG26
R SVD1
BG22
R SVD2
SB_VR EFDQ BG7
BF23 R SVD3 BG57
10mil
R SVD4 VSS_NC TF1
BE26 BG5
R SVD5 VSS_NC TF2
BE24 BE58
R SVD6 VSS_NC TF3
BE22 BE4
R SVD7 VSS_NC TF4
SA_VR EFDQ BE7 BD59
R SVD8 VSS_NC TF5
BD26 BD3
10mil
R SVD9 VSS_NC TF6
BD25 BC61
R SVD10 VSS_NC TF7
BD22 E61
R SVD11 VSS_NC TF8
BD21 E1
BB21 R SVD12 VSS_NC TF9 D 59
R SVD13 VSS_NC TF10
BB19 C 58
BA22 R SVD14 VSS_NC TF11 C 3
R SVD15 VSS_NC TF12
BA19 A57
R SVD16 VSS_NC TF13
AY 22 A5
R SVD17 VSS_NC TF14
AY 21
R SVD18
AV19
R SVD19
AU21
R SVD20
AU19
R SVD21
AT49
R SVD22
AT21
R SVD23
AM15
R SVD24
AM14 N 59
AH2 R SVD25 BCLK_ITP N 58
R SVD26 BCLK_ITP#
AG13
R SVD27
W14
R SVD28
U14
R SVD29
P13
R SVD30
N50
R SVD31
N42
R SVD32
M14
R SVD33
M13
R SVD34
L47
R SVD35
L45
L42 R SVD36
R SVD37
K48
R SVD38
K24
R SVD39
H48
R SVD40
P31X24_1023B_01B
Schematic Diagrams
Sheet 8 of 44
Processor 7/7
Processor 7/7 B - 9