Advertisement
IC DESCRIPTION-1/3 (LA9241ML)-2/2
QQ
3 7 63 1515 0
Pin No.
Pin Name
35
TOFF
36
TES
37
HFL
38
SLOF
39, 40
CV–, CV+
41
RFSM
42
RFS–
43
SLC
44
SLI
45
DGND
46
FSC
47
TBC
48
NC
49
DEF
50
CLK
51
CL
52
DAT
53
CE
TE
L 13942296513
54
DRF
55
FSS
56
VCC2
57
REFI
58
VR
59
LF2
60
PH1
61
BH1
62
LDD
63
LDS
64
VCC1
www
.
http://www.xiaoyu163.com
I/O
I
Tracking off control signal input pin from DSP. Off when TOFF = H.
O
Pin from which TES signal is output to DSP.
"High Frequency Level" is used to judge whether the main beam position is on top of bit or on
O
top of mirror.
I
Sled servo off control input pin.
I
CLV error signal input pin from DSP.
O
RF output pin.
I
RF gain setting and EFM signal 3T compensation constant setting pin together with RFSM pin.
O
"Slice Level Control" is the output pin which controls the RF signal data slice level by DSP.
I
Input pin which control the data slice level by the DSP.
—
Digital system GND.
O
Output pin to which external focus search smoothing capacitor is connected.
I
"Tracking Balance Control" EF balance variable range setting pin.
—
No connection.
O
Disc defect detector output pin.
I
Reference clock input pin. 4.23 MHz of the DSP is input.
I
Microprocessor command clock input pin.
I
Microprocessor command data input pin.
I
Microprocessor command chip enable input pin.
O
"Detect RF" RF level detector output.
I
"Focus Search Select" focus search mode (± search/+ search) select pin.
—
Servo system and digital system Vcc pin.
—
Pin to which external bypass capacitor for reference voltage is connected.
O
Reference voltage output pin.
I
Disc defect detector time constant setting pin.
I
Pin to which external capacitor for RF signal peak holding is connected.
I
Pin to which external capacitor for RF signal bottom holding is connected.
O
APC circuit output pin.
I
APC circuit input pin.
—
RF system Vcc pin.
x
ao
u163
y
i
http://www.xiaoyu163.com
2 9
8
Description
Q Q
3
6 7
1 3
1 5
co
.
-24-
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9
Advertisement
