Harman Kardon AVR354 Service Manual page 55

AVR354
BLOCK DIAGRAM
A3S56D30ETP
Type Designation Code
A 3 S 56 D 3 0 E TP –G5
DLL
Memory Memory
Array Array
Bank #0 Bank #1
Mode Register
Address Buffer
A0-12
BA0,1
CLK
256M Double Data Rate Synchronous DRAM
DQ0 - 7
I/O Buffer
Memory
Array
Bank #2
Control Circuitry
Control Signal Buffer
Clock Buffer
/CS /RAS /CAS /WE
/CLK
CKE
This rule is applied to only Synchronous DRAM family.
6: 166MHz @CL=3.0/2.5, and 133MHz @CL=2.0
Speed Grade
5: 200MHz @CL=3.0, 166MHz @CL=2.5, and 133MHz @CL=2.0
5E: 200MHz @CL=3.0/2.5, and 133MHz @CL=2.0
Package Type TP: TSOP(II)
Process Generation
Function Reserved for Future Use
Organization 2 n 3: x8
DDR Synchronous DRAM
Density 56: 256M bits
Interface S:SSTL_3, _2
Memory Style (DRAM)
Zentel DRAM
115
A3S56D30ETP
A3S56D40ETP
DQS
DQS Buffer
Memory
Array
Bank #3
DM
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