Atmel ATA6264 Specification Sheet
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Atmel ATA6264 Specification Sheet

Atmel ATA6264 Specification Sheet

Atmel airbag power supply ic specification sheet preliminary
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Features

•
Maximum Supply Voltage 40V
•
One Programmable/Adjustable Boost Converter
•
Two Programmable Buck Converters
•
One Programmable Linear Regulator
•
OTP Customer Mode
•
16-bit Serial Interface
•
Two ISO9141 Interfaces (One Interface Programmable to LIN Functionality)
•
Watchdog
•
Various Diagnosis Functions
•
5 Voltage Sources Tailored to Resistor Measurement
•
Charge Pump
•
Small, 44-pin Package
•
ESD Protection Against 2kV and 4kV

1. Description

With the introduction of the ATA6264, Atmel
power supplies for future airbag systems tailored to the needs of the automotive
industry. It is designed in Atmel's 0.8 micron BCDMOS technology. ATA6264 contains
all the necessary blocks to supply the microcontroller, the firing capacitors, and
peripheral components of the airbag system. The power supply specifically fulfills the
power requirements of dual-voltage microcontrollers used in modern ECUs. The inte-
grated watchdog and diagnosis blocks additionally support the safety aspects. The
8-MHz 16-bit SPI enables a high communication speed. Despite the high-level func-
tionality, ATA6264 comes in a space-saving QFP44 package.
®
introduces a new generation of airbag
Airbag Power
Supply IC
ATA6264
Preliminary
4929B–AUTO–01/07

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Summary of Contents for Atmel ATA6264

  • Page 1: Features

    With the introduction of the ATA6264, Atmel power supplies for future airbag systems tailored to the needs of the automotive industry. It is designed in Atmel’s 0.8 micron BCDMOS technology. ATA6264 contains all the necessary blocks to supply the microcontroller, the firing capacitors, and peripheral components of the airbag system.
  • Page 2 Serial Interface Watchdog RESQ2 Reset GNDD TxD1 RxD1 TxD2 RxD2 ISO9141 IASG1 IASG2 IASG3 IASG4 IASG5 ISENS GNDA BATT ATA6264 [Preliminary] SVSAT VSAT CP Logic IASG AMUX Internal Supply Reference GKEY- Logic GEVZ OCEVZ EVZ- Regulator GNDB FBEVZ COMEVZO SVSAT...

  • Page 3: Block Description

    100 mA. The user can program the voltage via an OTP system. With a sophisticated power-sequencing concept of VCORE and VPERI, ATA6264 sup- ports dual-voltage-supply microcontrollers, so that under all conditions the voltage difference between the two linear regulator voltages never drops below a defined value.

  • Page 4: Pin Configuration

    Clock input of the serial interface MOSI Data input of the serial Interface RESQ2 Redundant reset output IREF Connection for the external reference resistor Analog measurement output ATA6264 [Preliminary] 44 43 42 41 38 37 35 34 IASG1 IASG2 IASG3 IASG4...
  • Page 5 OCEVZ Input for overcurrent measurement of the EVZ regulator GEVZ Gate driver output for the external FET of the EVZ regulator GNDB GND connection of all power stages COMEVZO Output of the EVZ externally compensated error amplifier 4929B–AUTO–01/07 ATA6264 [Preliminary]...

  • Page 6: Absolute Maximum Ratings

    SCLK, VINT) Current at logic pins ESD classification at pins connected to devices outside the ECU (K30, K15) Human body model (HBM) ATA6264 [Preliminary] Remark Any combination of one or more pins applied with any voltage between the limits K30 and K15 connected via diode to V USP connected via minimum 5 k to V (maximum reverse current 5 mA).
  • Page 7 Human body model (HBM) Charged device model (CDM) – no corner pins Charged device model (CDM) – corner pins 4929B–AUTO–01/07 Remark AEC Q100-002 AEC Q100-002 AEC Q100-002 ESD STM5.3.1-1999 ATA6264 [Preliminary] Minimum Maximum ±3000 ±2500 ±1500 ±500 ±750 Unit...

  • Page 8: Functional Range

    4. Functional Range Within the functional range, the ATA6264 works as specified. All voltages are referenced to the ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins. At the beginning of each specification table, supply voltage and temperature conditions are described.

  • Page 9: Protection Against Substrate Currents

    Protection Against Substrate Currents Due to the fact that the ATA6264 is connected to the wiring harness and to components outside of the ECU, negative voltages at the following pins might occur: • IASG interface: • USP comparator: If substrate currents occur, it is guaranteed by design that no disturbance and malfunction of the following blocks and functions will happen: •...

  • Page 10: Supply Currents

    0V < V VCORE measurement VCORE active *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6264 [Preliminary] = 18V, = 3V and KEYLATCH = OFF = 40V,...

  • Page 11: Discharger Circuit

    (IP). The memory cells are one-time programmable (OTP) and cannot be changed after the IP (default values are “0”). In general, the IP is done after mounting the ATA6264 on the PCB with an in-circuit tester. The programming voltage of 11.7V has to be applied on pin VSAT.
  • Page 12 The following settings can be made at the initial programming: MSBit Table 5-2. ISO/LIN ATA6264 [Preliminary] Initial Programming Settings Set to 0 No external transistor at VPERI (default) Set to 0 ISO9141 mode is activated at K1 (default) ISO/LIN Parity...
  • Page 13 RESQ2 and TxD2 to 5V Transmit 5A5A(h) via SPI to Enable Testmode Wait until VSAT = 11.7V Transmit IP command A9xx(h) via SPI to configure ATA6264 Wait 1 ms Remove all voltages and pinloads to get out of Test mode ATA6264 [Preliminary]...

  • Page 14: Start-Up And Power-Down Procedure

    Start-up and Power-down Procedure The ATA6264 is powered via the pin K30 (battery voltage) and via a diode or a resistor it is con- nected to the ignition key line K15. In order to detect an interruption on one of these pins correctly, resistors are implemented at these pins.

  • Page 15: Start-Up Procedure If Vvcore Is Programmed To Be 5V Or 2.5V

    Depending on the initial programming of the ATA6264, the start-up procedure takes place in dif- ferent phases. 5.3.1 Start-up Procedure if V Phase1: After switching on the ignition key, K15 voltage will apply at pin K15. If, in addition, the voltage at pin K30 is larger than 3.85V to 5V, the EVZ regulator will be enabled.

  • Page 16: Start-Up Procedure If Vvcore Programmed To Be 1.88V

    Phase2: If VEVZ is larger than 7.5V to 9V, the VSAT regulator starts operating. Phase3: After VVSAT has reached 6.77V to 7.2V, the VPERI regulator starts working. Phase4: If VVPERI is higher than 1.25V to 1.7V, the VCORE regulator will be enabled. ATA6264 [Preliminary] Start-Up and Power-Down Procedure if V 3V to 4.15V GEVZ 7.5V to 9V...

  • Page 17: The Power-Down Procedure For Vvcore Is Programmed To Be 1.88V

    Start-up and Power-down Procedure if V 3V to 4.15V GEVZ 7.5V to 9V VSAT VPERI VCORE ATA6264 [Preliminary] Programmed to Be 1.88V VCORE 3V to 4.15V too low EVZ voltage 5.5V to 6.2V VSAT goes into On Mode charge pump deactivated 6.77V to 7.2V...

  • Page 18: Power Supply Sequencing

    (Only active when initial programming sets V In order to meet the requirements of several dual-voltage-supply microcontrollers, a power-sequencing function is implemented. The ATA6264 ensures that the voltage difference VPERI – VCORE will not exceed 2.8V. The voltage difference between VPERI and VCORE is monitored. In error cases, for example, if the VCORE regulator does not start to work, the difference may rise above the 2.8V threshold.
  • Page 19 4929B–AUTO–01/07 K15GOOD Comp IREF lost signal K30GOOD EVZEN Comp CORESWAP Comp EVZGOOD Comp VSATGOOD Comp Delta < 2.8V - Regulator CORE ATA6264 [Preliminary] VEVZ VK30 GEVZ VEVZ driver VSAT SVSAT driver VSAT VEVZ VPERI SVPER driver VPERI SVCORE VCORE VSAT...

  • Page 20: Charge Pump

    SPI. It is capable of 250 µA. Figure 7-1. Block Diagram Charge Pump External circuit CP-Out VSAT SVSAT Status Status register register Serial interface I = 1.4 mA Note: 1. Connected to the drivers (see Figure 5-3) ATA6264 [Preliminary] 4929B–AUTO–01/07...
  • Page 21 = 5.5V to 40V, < V = –100 µA CP_Out (current consumption of and V have to CORE be added) ATA6264 [Preliminary] > 3V, V = 3.7V to 5.47V VINT = –40°C to 150°C Symbol Typ. Max. –0.8 –4.2...

  • Page 22: Gkey Function

    K30 voltage determines the EVZ Enable signal. In order to achieve the Switch Function of the GKEY function, a transformer has to be used. Table 8-1. Note: Figure 8-1. ATA6264 [Preliminary] Overview of the Start-up Conditions High High High 1. Less than the value shown in number 7.3 of 2.
  • Page 23 PERI CORE Section 4. ”Functional Range” on page Test Conditions increasing, > 5V increasing, > 4.15V 0V V 40V, AMUX measurement EVZ active ATA6264 [Preliminary] BATT GEVZ OCEVZ GNDB FBEVZ = –40°C to 150°C Symbol Typ. 3.85 Max. Unit Type* 4.15...

  • Page 24: Evz Step-Up Regulator

    An inductor is PWM-switched by an external n-channel power FET with a fixed frequency of 100 kHz. A driver stage for the external FET is integrated into the ATA6264. The current limita- tion of the external FET is implemented by using an external resistor in series between the source connection of the external FET and GND, sensing the voltage drop at this resistor via the pins OCEVZ and GNDA.
  • Page 25 The pins EVZ and FBEVZ have to be shorted in applications without an external divider in order to ensure a safe operation of the ATA6264 in the case of an EVZ-pin fault. If the voltage at pin FBEVZ is larger than the voltage at pin EVZ, the ATA6264 switches the feedback path automat- ically to pin FBEVZ.
  • Page 26 FET exceeds a certain level, determined by the voltage drop across an external resistor in the range of 0.2 . The ATA6264 itself will see a voltage at the OCEVZ pin. If this voltage exceeds typically 0.5V, the output transistor conduction has to be suppressed.
  • Page 27 < 8V or 4V < V < 8V GEVZ (after startup) GEVZ programmed EVZExt VEVZ (via external divider) ATA6264 [Preliminary] = 200 pF to 2 nF, V = 3.7V to 5.47V = –40°C to 150°C Symbol Typ. Max. –5% GEVZ –10%...
  • Page 28 Temperature shutdown 8.31a activation Hysteresis for reactivation of 8.31b GEVZ *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6264 [Preliminary] Test Conditions programmed VEVZ EVZ1 programmed VEVZ...
  • Page 29 COMEVZO = 100 µA COMEVZO COMEVZO = –100 µA COMEVZO COMEVZO – V GNDA GNDA GNDD GNDA – V GNDB GNDB GNDD ATA6264 [Preliminary] Symbol Typ. Max. COMEVZO –1000 –150 COMEVZO –10 COMEVZO VINT – VINT COMEVZO 0.3V GNDA GNDB...

  • Page 30: Vsat Power Supply

    PWM-switched with a frequency of 200 kHz via an internal high-side DMOS power transistor. The VSAT power supply is connected to the boost converter output (EVZ), and uses the stored energy of the boost converter capacitor if the voltage at K30 is missing. The regulator uses both current and voltage feedback.
  • Page 31 SVSATmin – V EVZmax SVSATmin VSAT Time between reaching overvoltage and reaching SVSAT 90% of V maximum SVSAT under on condition ATA6264 [Preliminary] = 3.7V to 5.45V = –40°C to +150°C Symbol Typ. Max. SVSAT SVSAT –5% SVSAT –10% +10%...
  • Page 32 1. Depending on implementation of slope compensation; sub-harmonics must be prevented 2. The value of the minimum load current must be higher than the internal pull-up current at pin VSAT to ensure proper func- tion of the regulator ATA6264 [Preliminary] Test Conditions Time between reaching...

  • Page 33: Vperi Power Supply

    The VPERI voltage can be programmed via the serial interface to one of two different voltage values during initial programming. 4929B–AUTO–01/07 regulator a stabilized and ripple-free voltage is generated out of the VSAT supply PERI Peripheral Peripheral Linear regulator SVPERI Peripheral Linear regulator VPERI ATA6264 [Preliminary] Regulator VSAT SVPERI Peripheral VPERI VSAT Peripheral...
  • Page 34 10.7 Line regulation 10.8 Load regulation 10.10 Supply voltage rejection *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6264 [Preliminary] = 3.7V to 5.47V, V CORE and V...

  • Page 35: Vcore Power Supply

    (pin CP). 4929B–AUTO–01/07 Control- signal K30/EVZ Slope compensation Comp. Error amp. Slope compensation ATA6264 [Preliminary] Current measurement and leading edge blanking Overcurrent SVCORE Logic and driver Overvoltage Current measurement and leading edge...
  • Page 36 1. Depending on implementation of slope compensation, sub-harmonics have to be prevented. 2. The value of the minimum load current must be higher than the internal pull-up current at pin VCORE to ensure proper function of the regulator. ATA6264 [Preliminary] = 5.5V to 40V, V – 0.3V, V = 3.7V to 5.47V...
  • Page 37 Output transistor off SVCORE COMCOO COMCOO = 1.88V CORE COMCOI = 2.5V/5V CORE = 165 µA COMSATO COMCOO = –85 µA COMSATO COMCOO ATA6264 [Preliminary] Symbol Typ. Max. SVCOREoff SVCOREoff SVCOREoff –10 SVCORE 3000 COMCOO –165 –85 COMCOO COMCOI –10 COMSATO VINT –...
  • Page 38 1. Depending on implementation of slope compensation, sub-harmonics have to be prevented. 2. The value of the minimum load current must be higher than the internal pull-up current at pin VCORE to ensure proper function of the regulator. ATA6264 [Preliminary] Test Conditions increasing See number 7.3 of...

  • Page 39: Usp Comparator For General Purpose

    Section 4. ”Functional Range” on page Test Conditions = 2.44V = 0 to 40V Trigger voltage for status register bit 7= high with increasing V ATA6264 [Preliminary] to AMUX Status register > reset threshold, V = 3.7V to 5.47V CORE = –40°C to 150°C Symbol Typ.

  • Page 40: Reference Voltage And Reference Current Generation

    13.3b Voltage at VINT 13.3c Voltage at VINT 13.3d Voltage at VINT *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6264 [Preliminary] Truth Table for VINT K30GOOD K15GOOD >...

  • Page 41: Reset Function (Pin Resq And Pin Resq2)

    15. Reset Function (Pin RESQ and Pin RESQ2) Pins RESQ and RESQ2 are low-active digital outputs of the ATA6264, which provide a digital “low” signal in the case of a missing or incorrect watchdog transmission or in the case of improper VEVZ, VPERI or VCORE voltage.
  • Page 42 CORE RESQ chip internal trigger window communication RESQ2 * Watchdog cycle, see pages 48 and 49 ATA6264 [Preliminary] 16 ms 4 ms 4 ms 16 ms WD cyc* Re-configure prescaler while 1 st and 2nd trigger watchdog WD cyc* command...
  • Page 43 EVZ smaller than or equal to 10 µs to 20 µs do not influence the RESQ or RESQ2 pins. If the ATA6264 internal supply voltage (VINT) is below its proper value, RESQ and RESQ2 are also set to low.
  • Page 44 Figure 15-4. Application Example Necessary for operation: = 5.5V to 40V, V Operating conditions of all other supply pins: Other pins: As defined in ATA6264 [Preliminary] VEVZ (no trigger has occurred) EVZGOOD = high (trigger occurred 1 = OK) Incorrectly triggered...
  • Page 45 5V VPERI VPERI is set to 3.3V VPERI VPERI is set to 5V VPERI VPERI is set to 3.3V VPERI VPERI rising falling ATA6264 [Preliminary] Symbol Typ. Max. RESQ VPERI VPERI – 0.8 RESQ2 RESQ RESQ2 5.03 VCORE 0.17 VCORE 2.25...
  • Page 46 RESQ2 14.21 Rise time RESQ, RESQ2 14.22 Fall time RESQ, RESQ2 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6264 [Preliminary] Test Conditions RESQ RESQ2 RESQ is switched to low = 0.4V),...

  • Page 47: Watchdog Function

    Features: • Watchdog trigger has to be done via the serial interface • In case of a watchdog-trigger mismatch, the ATA6264 is set into its default state (latches, MISO status, etc.) and RESQ is set to low. • Watchdog has to be triggered cyclically (prescaler for repetition time is set via serial interface command).
  • Page 48 Any further configuration inside or outside this time window will cause an immediate reset via RESQ. Figure 16-2. Reconfiguration Prescaler Functional Principle reconfiguration RESQ chip internal trigger window Serial interface communication ATA6264 [Preliminary] Succesful No succesful reconfiguration inactive 1 ms active 1 ms 4929B–AUTO–01/07...
  • Page 49 Cyclic phase: Between two trigger commands a different SPI command must be seen by the SPI decoder Figure 16-3. Watchdog Trigger Functional Principle (Successful Watchdog Trigger) interface communication 4929B–AUTO–01/07 RESQ chip t_retrigger internal trigger window Serial ATA6264 [Preliminary] inactive t_retrigger t_retrigger...
  • Page 50 Figure 16-4. Watchdog Trigger Functional Principle (Unsuccessful Watchdog Trigger) Serial interface communication Serial interface communication ATA6264 [Preliminary] RESQ inactive t_retrigger chip internal trigger window RESQ inactive t_retrigger chip internal trigger window inactive active t_retrigger inactive active t_retrigger active active 4929B–AUTO–01/07...
  • Page 51 The status of the watchdog prescaler is indicated in the status register. 4929B–AUTO–01/07 MSByte a, b, and c to be set as defined in Table 16-1 Watchdog Prescaler Command Selection Bits ATA6264 [Preliminary] LSByte Retrigger Time (ms) Set to default (16 ms) Set to default (16 ms) Hex Code 60Fx...
  • Page 52 Time for RESQ = low after 15.9 watchdog timeout *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6264 [Preliminary] > Reset threshold CORE and V are within functional range limits, T VSAT Section 4.
  • Page 53 Figure 16-5. Watchdog Trigger 5.0V 4.75V RESQ 15.2 ms chip internal trigger window Serial interface communication 4929B–AUTO–01/07 15.4 ms 15.8 ms 15.3 ms 15.7 ms 15.6 ms 15.5 ms Re-configure prescaler during 1 st and 2nd trigger watchdog command ATA6264 [Preliminary] 15.9 ms...

  • Page 54: Lin/Iso 9141 Interfaces

    17. LIN/ISO 9141 Interfaces The ATA6264 includes two complete ISO 9141 interfaces. Interface #1 is controlled via the pins RxD1 and TxD1, interface #2 is controlled via the pins RxD2 and TxD2. In order to support both ISO9141 and LIN bus requirements, interface #1 can be configured during initial programming.
  • Page 55 (x = 1, 2) = 3.3V), PERI (x = 1, 2) = 3.3V), PERI (x = 1, 2) (x = 1, 2) (x = 1, 2) (x=1, 2) ATA6264 [Preliminary] Symbol Typ. Max. –35 –50 –65 TxDx 0.07 –10 VPERI...
  • Page 56 16.36 = low *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6264 [Preliminary] Test Conditions (x = 1, 2), measured from TxD H to L to K = 0.9...
  • Page 57 K30 > 15V to 25V K30 > 25V to 40V (x = 1, 2), output driver deactivated, AMUX measurement deactivated K30 = 5.5V to 40V = –25V Baudrate PDtL PDtH PDkL ATA6264 [Preliminary] Symbol Typ. Max. PDkH –1 SYM_T1 –1 SYM_R1 –10 +100 –10...

  • Page 58: Voltage/Current Sources (Iasgx Sources)

    The five IASG pins are connected to the analog multiplexer block via different dividers. Voltages applied to these IASG pins can be measured at the UZP pin, selected via SPI commands. ATA6264 [Preliminary] Sources) can be calculated using the following formulas: –...
  • Page 59 VSAT S e c t i o n 4 . ” F u n c t i o n a l R a n g e ” o n p a g e 8 ISENS ATA6264 [Preliminary] Current mirror Serial...
  • Page 60 17.9 Settling time 17.10 Switch-on delay *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6264 [Preliminary] Test Conditions (x = 1 to 5), –40 mA < I <...
  • Page 61 ISENS VPERI active) = 0V to 0.96 ISENSE ISENS VPERI (x = 1 to 5) IASGx channel deactivated, IASG 0V < V < V IASGx ATA6264 [Preliminary] Sources) Symbol Typ. Max. 0.96 1.05 ISENSE VPERI VPERI –1.6 +1.6 ISENSE –1.6 +1.6...

  • Page 62: Amux (Analog Multiplexer For Voltage Measurements)

    19. AMUX (Analog Multiplexer for Voltage Measurements) Various voltages and the chip temperature inside of the ATA6264 can be measured at the ana- log measurement output UZP. Different voltage dividers ensure that the values of the measured voltages at UZP are in the range of 0V to V face command has to be sent to the ATA6264.
  • Page 63 For V = 5V (> 3V to 25V) VPERI For V = 3.3V (1.5V to 3V) VPERI For V = 3.3V (> 3V to 25V) VPERI ATA6264 [Preliminary] Symbol Typ. Max. –5 UZPoffset 6.05 ± 4% Ratio 6.05 ± 2.3% 9.12 ±...
  • Page 64 1 buffer 18.23 Ratio V *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6264 [Preliminary] Test Conditions For V = 5V (1.5V to 3V)

  • Page 65: Uzp Buffer

    20. UZP Buffer The pin UZP is an analog output pin of the ATA6264. The UZP buffer is realized as a tristate out- put with the ability to drive to VPERI as well as to GNDA. The selected measurement result is given to the pin UZP as long as no new measurement is selected or the tristate command has been sent.
  • Page 66 19.9 Output capacitance 19.10 Time to switch to tristate mode *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6264 [Preliminary] Test Conditions = 0V, UZP connected to GND...

  • Page 67: Chip Temperature Measurement

    Test Conditions Chip temperature switched via AMUX to UZP Chip temperature switched via AMUX to UZP, T = 25°C If overtemperature is detected, voltage drops by 35 mV ATA6264 [Preliminary] = –40°C to 150°C Symbol Typ. Max. –4 –3.6 –3.2 1.29 1.54...

  • Page 68: Serial Interface Commands

    The pin SSQ (low active) is used to select the ATA6264. If pin SSQ is inactive (high), the output pin MISO is disabled (tristate) and the signals at the pins SCLK and MOSI are ignored and do not affect the data in the serial interface register.
  • Page 69 = 0 mA to 1 mA MISO MISO = 5V MISO VPERI = 5V MISO VPERI SSQ, SCLK, MOSI Switched-off condition MISO Switched-off condition MISO ATA6264 [Preliminary] Symbol Typ. Max. MISOMSB_V MISOV MISOhiZ nodata SCLK –95 –45 pu_SSQ –95 –45 pu_SCLK VPERI 0.25...

  • Page 70: Set Commands

    Serial interface commands other than those listed in tion of measurements via AMUX, cause pin UZP to be switched to tristate, and IASG sources to be deactivated. The status of the latches does not change. ATA6264 [Preliminary] 4. (< 20 ns) 5. (> 20 ns) 6.
  • Page 71 Because the K1 and K2 interfaces are by default switched to ISO (LIN) mode, the commands 9CF0, 9CFF, 9C00, and 9C0F default to invalid commands. 4929B–AUTO–01/07 Key Latch Commands MSByte Watchdog Commands MSByte Switch Commands MSByte ATA6264 [Preliminary] LSByte LSByte LSByte Hex Code 3FFF 3000 Hex Code 6A55...
  • Page 72 Description Write data to IP register The initial programming command is only available in Test mode. For more information about the programming flow and the register contents, see ATA6264” on page Table 22-7. Description Set UZP to tristate mode and switch off all...
  • Page 73 IASG number in binary format; only 001 = IASG1, 010 = IASG2, 011 = IASG3, 100 = IASG4, and 101 = IASG5 are valid commands Example MSByte ATA6264 [Preliminary] LSByte LSByte LSByte Hex Code...

  • Page 74: Serial Interface Status Register

    Serial Interface Status Register For all serial interface commands except the test-mode commands (55AAh, AA55h, 5500h), the ATA6264 status is available at the MISO line. For the status register a 16-bit structure is used, one bit for each information. Table 22-10. Status Register MSBit Table 22-11.
  • Page 75 SPI command, unless overtemperature still exists. In the case of a reset, bits b4 and b5 are not set to their default state. These bits show the status before reset so that the microcontroller can detect whether or not the ATA6264 is in power-up state.

  • Page 76: Test Mode

    23. Test Mode For better testability of the ATA6264, a test mode is implemented. This mode is activated if the pins RESQ and TxD1 are connected to GND, the pins RESQ2 and TxD2 are connected to VPERI, and the serial interface command 5A5Ah is sent to the ATA6264. Test mode is latched...

  • Page 77: Application Circuits

    D, L, C SVCORE VCORE COMCOI COMCOO Firing ASIC Firing loops 4929B–AUTO–01/07 IASG1 to 5 IREF IASG1 to 5 RESQ2 RxD2 TxD2 RxD1 TxD1 RESQ GNDD ISENS GNDA CP-OUT Enable Enable ATA6264 [Preliminary] Micro- Sensor controller Serial interface Safety- system monitoring...
  • Page 78 Figure 24-2. Typical Application Circuit ATA6264 ATA6264 [Preliminary] 4929B–AUTO–01/07...

  • Page 79: Ordering Information

    Package: P-TQFP 44 (acc. JEDEC OUTLINE No. MO-112) Dimensions in mm Drawing-No.: 6.543-5131.01-4 Issue: 1; 11.05.06 4929B–AUTO–01/07 Package P-TQFP44 P-TQFP44 ±0.2 ±0.05 +0.08 0.37 -0.07 technical drawings according to DIN specifications ATA6264 [Preliminary] Remarks Tray Taped and reeled ±0.05 ±0.05...

  • Page 80: Revision History

    Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4929B-AUTO-01/07 ATA6264 [Preliminary] History Put datasheet in a new template Section 23 “Test Mode” on page 76 changed...

  • Page 81: Table Of Contents

    Linear Regulator VPERI ...3 1.1.5 Blocks Included ...3 Protection Against Substrate Currents ...9 Discharger Circuit ...11 Initial Programming of the ATA6264 ...11 Start-up and Power-down Procedure ...14 5.3.1 Start-up Procedure if VVCORE is Programmed to Be 5V or 2.5V ...15 5.3.2 The Power-down Procedure Takes Place in Different Phases ...15...
  • Page 82 23 Test Mode ... 76 24 Application Circuits ... 77 25 Ordering Information ... 79 26 Package Information ... 79 27 Revision History ... 80 ATA6264 [Preliminary] 22.1 Overview ...68 22.2 Set Commands ...70 22.3 Serial Interface Status Register ...74 4929B–AUTO–01/07...
  • Page 83 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

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