Sony ICF-CD523 Service Manual page 30

Fm/am cd kitchen clock radio
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ICFCD523
Ver. 1.1
• IC Pin Function Description
MAIN BOARD IC401 uPD789406AGC-044-8BT-A (SYSTEM CONTROLLER)
Pin No.
Pin Name
1
VDD1
2
BIAS
3 to 5
VLC0 to VLC2
6
VSS1
7 to 10
COM0 to COM3
11 to 26
SEG0 to SEG15
27 to 30 SEG16 to SEG19
31
NC
32
B MUT
33
C RST
34
KS4
35 to 38
KS0 to KS3
39
AVDD
40
AVREF
41
VERSION0
42
VERSION1
43
CLOSE SW
44
OPEN SW
45
C SENS2
46
C SENS1
47
C SQSO
48
AVSS
49
SCOR
50
C MUT
51
C SQCK
52
AC IN
53
BUZZER
54
C CLK
55
C LAT
56
C DATA
57
M MUT
58
AMUT
59
CD ON
60
RADIO ON
61
R DATA
62
R CLK
63
R LAT
64
POWER ON
65
SHIFT0
66
SHIFT1
67
RESET
68
X2
69
X1
30
I/O
-
Power supply terminal (+5V)
O
Bias output for the liquid crystal display drive
-
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
-
Ground terminal
O
Common drive signal output to the liquid crystal display
O
Segment drive signal output to the liquid crystal display
O
Segment drive signal output terminal Not used
-
Not used
O
Buzzer sound muting on/off control signal output terminal Not used
O
System reset signal output to the RF amplifier and digital signal processor "L": reset
O
Key strobe signal output to the key matrix
O
Key strobe signal output to the key matrix
-
Power supply terminal (+5V) (for A/D converter)
-
Reference voltage (+5V) terminal (for A/D converter)
I
Destination setting terminal "L": US and Canadian models, "H": AEP model
I
Destination setting terminal Fixed at "L" in this set
I
Disc tray close detection switch input terminal "H": disc tray is closed
I
Disc tray open detection switch input terminal "H": disc tray is opened
I
Internal status signal (sense signal) input from the RF amplifier
I
Internal status signal (sense signal) input from the digital signal processor
I
Subcode Q data (80 bit serial) input from the digital signal processor
-
Ground terminal (for A/D converter)
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
O
Digital muting on/off control signal output to the digital signal processor "H": muting on
O
Subcode Q data (80 bit serial) reading clock signal output to the digital signal processor
I
Power failure detection input terminal "L": power failure, "H": power on
O
Buzzer sound drive signal output terminal
O
Serial data transfer clock signal output to the digital signal processor
O
Serial data latch pulse signal output to the digital signal processor
O
Serial data output to the digital signal processor
O
Muting on/off control signal output terminal Not used
At initial mode: Setting terminal for the test mode (CD manual mode) "L" CD manual mode
I/O
At normal mode: Audio muting on/off control signal output terminal "L": muting on
At initial mode: Setting terminal for the test mode (CD auto mode) "L": CD auto mode
I/O
At normal mode: Power on/off control signal output for the CD +5V power supply
"L": CD power on
O
Power on/off control signal output for the radio +5V power supply "L": radio power on
O
PLL serial data output to the FM/AM PLL
O
PLL serial data transfer clock signal output to the FM/AM PLL
O
PLL serial data latch pulse signal output to the FM/AM PLL
O
Front side speaker on/off control signal output to the power amplifier "H": speaker on
O
Shift clock output terminal of the main system clock (4.19 MHz) Not used
O
Shift clock output terminal of the main system clock (4.19 MHz) Not used
System reset signal input from the reset signal generator "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
O
Main system clock output terminal (4.19 MHz)
I
Main system clock input terminal (4.19 MHz)
Description
Not used

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