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3 7 63 1515 0
LSI PIN DESCRIPTION
ZFX-2 (XY297A00) DSP
PIN
NAME
NO.
1
ED2
2
ED3
3
ED4
4
ED5
5
ED6
6
ED7
7
VSS
8
VDD
9
CLKM0
10
CLKM1
11
TMS
12
TDI
13
TCK
14
CLKIN
15
VSS
16
VDD
17
CLKO
18
EA12/ED8
19
EA13/ED9
20
EA14/ED10
21
EA15/ED11
22
VSS
23
VDD
24
EA16/ED12
25
EA17/ED13
26
EA18/ED14
TE
L 13942296513
27
EA19/ED15
28
EA4/ED16
29
EA5/ED17
30
EA6/ED18
31
EA7/ED19
32
VSS
33
VDD
34
EA8/ED20
35
EA9/ED21
36
EA10/ED22
37
EA11/ED23
38
TEST0
39
TEST1
40
TEST2
41
TEST3
42
/BIO
43
/INT1
44
ARBC1
45
ARBC2
46
AX1
47
AX2
48
AX3
49
VSS
50
VDD
Z: High inpedance
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http://www.xiaoyu163.com
I/O
FUNCTION
I/O
I/O
External Memory and I/O Data Bus
I/O
I/O
I/O
I/O
-
Ground
-
Power Supply
I
Clock Mode
1 min. 3fold 5fold PLL BYPASS
CLKM0
0
1
0
I
CLKM1
0
0
1
I
TAP(Test Access Port) Mode Select
I
TAP Data Input
I
TAP Clock
I
Master Clock
-
Ground
-
Power Supply
O
Machine Clock Output
I/O
I/O
External SRAM and ROM Address Bus/ External DRAM and I/O Data Bus
I/O
I/O
-
Ground
-
Power Supply
I/O
I/O
External SRAM and ROM Address Bus/ External DRAM and I/O Data Bus
I/O
I/O
I/O
I/O
External Memory Address Bus/ External I/O Data Bus
I/O
I/O
-
Ground
-
Power Supply
I/O
I/O
External Memory Address Bus/ External I/O Data Bus
I/O
I/O
I
I
Test Mode Control
I
I
I
Separate Control Input
I
Interrupt 1
I
Audio Data Receive Unit 1 bit Clock
I
Audio Data Receive Unit 2 bit Clock
O
Audio Data Transmitt Unit 1 Data Output
O
Audio Data Transmitt Unit 2 Data Output
O
Audio Data Transmitt Unit 3 Data Output
-
Ground
-
Power Supply
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http://www.xiaoyu163.com
2 9
8
PIN
NAME
NO.
51
HX/SDA
52
/EMPTY
53
AXLR2
54
AR1
55
AR2
56
HRBCK/SA0
57
HR/SA1
58
HRS/SA2
59
VSS
60
VDD
1
61
HXBCK/SCL
1
62
HXS/SA3
63
/CS/SA4
64
HBCKS/SA5
65
I
2
CSEL
66
VSS
67
VDD
68
AXBC1
69
AXBC2
70
AXLR1
71
DIV8
72
/LAV
73
/LMV
74
/DRDY
75
EMU0
76
EMU1
Q Q
77
TDO
3
6 7
1 3
1 5
78
DIV512
79
ARLR1
80
ARLR2
81
HDIR/SA6
82
SEL5V3V
83
/MUTE
84
/TRST
85
/RS
86
VSS
87
VDD
88
/IOE
89
/RAS/SRCS
90
/CAS/SROE
91
/ROME
92
/WE
93
EA0
94
EA1
95
EA2
96
EA3
97
VSS
98
VDD
99
ED0
100
ED1
co
.
9 4
2 8
I/O
FUNCTION
I/O/Z
Host Interface Data Output/I2C Bus Data
O/Z
CMEM Update Buffer and HR Resistor Empty Flag Output
I
Audi o Data Transmi t t Uni t 2/3 Left and Ri g ht Channel Frame Frequency Si g nal
I
Audio Data Receive Unit 1 Data Input
I
Audio Data Receive Unit 2 Data Input
I
Host Interface Receive Clock / I2C Bus Address 0
I
Host Interface Data Input/ I2C Bus Address 1
I
Host Interface Recei v e Data Frame Frequency Si g nal / I2C Bus Address 2
-
Ground
-
Power Supply
I
Host Interface Transmitt Clock/ I2C Bus Clock
I
Host Interface Transmi t t Data Frame Frequency Si g nal / I2C Bus Address 3
I
Host Interface Chip Select/ I2C Bus Address 4
I
HRBCK/HXBCK Active Edge Select/ I2C Bus Address 5
I
Host Interface Mode Select
-
Ground
-
Power Supply
I
Audio Data Transmitt Unit 1 bit Clock
I
Audio Data Transmitt Unit 2/3 bit Click
I
Audi o Data Transmi t t Uni t 1 Left and Ri g ht Channel Frame Frequency Si g nal
O
Machine Clock Output then 8 min.
O
Ruch ALU Overflow Frag Output
O
Ruch MAC Overflow Frag Output
O/Z
Host Interface Transmitt Data Ready Frag Output
I/O/Z
Emurator Interrupt 0
I/O/Z
Emurator Interrupt 1
O/Z
TAP(Test Access Port) Data Output
0 5
8
2 9
9 4
2 8
O
Machine Clock then512 min.
I
Audi o Data Recei v e Uni t 1 Left and Ri g ht Channel Frame Frequency Si g nal
I
Audi o Data Recei v e Uni t 2 Left and Ri g ht Channel Frame Frequency Si g nal
I
Host Interface Data Format Select/ I2C Bus Address 6
I
Input Level Control
I
Mute Control
I
TAP(Test Access Port) Reset
I
Hardware Reset
-
Ground
-
Power Supply
O
External I/O Enable
O
External DRAM Low Address Strove/External SRAM Chip Select
O
External DRAM Cul u mn Address Strove/External SRAM Output Enabl e
O
External ROM Enable
O
External Memory and I/O Wright Enable
O
O
External Memory and I/O Address Bus
O
O
-
Ground
-
Power Supply
I/O
External Memory and I/O Data Bus
I/O
m
EMX660
9 9
SUB: IC306
9 9
15
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