Aiwa IC-DP200 Service Manual page 23
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Also See for IC-DP200:
- Operating instructions manual (72 pages) ,
- Operating instructions manual (72 pages)
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Pin No.
Pin Name
17
FODD
18
HREF
19 ~ 26
UV7 ~ UV0
27
XCLK1
28
XCLK2
29
DVDD
30
DGND
31
DOGND
32
DOVDD
33
PCLK
34 ~ 41
Y7 ~ Y0
42
CHSYNC
43
AGND
44
AVDD
TE
L 13942296513
45
SCL
46
SDA
47
MID
48
SGND
IC, PCF8576CH
Pin No.
Pin Name
1
NC
2 ~ 7
S34 ~ S39
8 ~ 9
NC
10
SDA
11
SCL
12
SYNC
13
CLK
14
VDD
15
OSC
www
16 ~ 18
A0 ~ A2
19
SA0
.
20
VSS
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I/O
O
FODD: Odd field flag. Asserted high during the odd field, low during the even field. (Not used)
HREF: Horizontal window reference output.
O
HREF is high during the active pixel window, otherwise low.
O
UVn: Digital output UV bus. UVn used for 16-bit operation for outputting chrominance data.
XCLK1 and XCLK2 are the input/output of the on-chip video oscillator.
I
Nominal crystal clock frequency is 27MHz.
O
If an external clock is used, input to XCLK1, leave XCLK2 unconnected. (XCLK2 = Not used)
–
Digital power (+5V) pin.
–
Digital ground connection.
–
Digital output ground connection.
–
Digital I/O power (+5V) pin.
PCLK: Pixel clock output. By default, data is updated at the falling edge of PCLK
O
and is stable at its rising edge. PCLK runs at the pixel rate in 16-bit bus operations
and twice the pixel rate in 8-bit bus operations.
Yn: Digital output Y bus. In a 16-bit operation, the luminance data is clocked out of this bus
O
at the rate of one byte per pixel. In 8-bit operation, the luminance data and the chrominance data
is multiplexed to this bus.
O
CHSYNC: Digital output for either composite sync or horizontal sync signal.
–
Analog ground connection.
–
Analog power (+5V) pin.
I
I
C serial clock input with schmitt trigger.
2
I/O
I
C serial data, output is open-drain, input with schmitt trigger.
2
I
Multiple I
C slave ID enable. (Not used)
2
–
Sensing ground connection
I/O
–
Not connected.
O
LCD segment outputs. (Not used)
–
Not connected.
I/O
I
C bus serial data input/output.
2
I
I
C bus serial clock input.
2
I/O
Cascade synchronization input/output. (Not used)
I
External clock input. (Not used)
–
Supply voltage.
I
Oscillator input. (Connected to VSS)
I
I
C bus subaddress inputs. (Connected to VSS)
2
x
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I
I
C bus slave address input, bit 0. (Connected to VSS)
2
i
–
Logic ground.
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Description
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Description
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