Ic Pin Function Description - Sony HCD-CPX1 Service Manual

HCD-CPX1
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6-19. IC PIN FUNCTION DESCRIPTION

• MAIN BOARD IC401 M30622MGN-B08FP (SYSTEM CONTROLLER (CD MECHANISM CONTROL))
Pin No. Pin Name
1 LCD ON
2 RDS DATA
3 LCD CD
4 SIRCS IN/WAKE
5 LCD DATA
6 LCD CS
7 LCD CLK
8
BYTE
9
CNVSS
10 XCIN
11 XCOUT
12 RESET
13 XOUT
14 VSS
15 XIN
16 VCC
17
NMI
18 RDS CLK
19 CD SCOR
TE
L 13942296513
20 AC CUT
21 ST MUTE
22 ST CE
23 ST DATA OUT
24 CD PWM3
25 ST DATA IN
26 CD PWM2
27 ST CLK
28 CD PWM1
29 IIC CLK
30 IIC DATA
31 NO USE
32
CD SQSO
33 CD SQCLK
34 ST STEREO
35
CD DATA
36 CD XLT
37 CD CLK
38 TC PLAY SW
39 32K OUT
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40
TC LINE MUTE
41
TC REC/MUTE
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42 TC BIAS-ON
43 TC PB/REC
44
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I/O
O
Power on/off control signal output for liquid crystal display "H": power on
I Serial data input from the RDS decoder Not used
Signal output for discriminating between command and display data to the liquid crystal display
O
driver "L": display data, "H": command
I
Remote control signal input terminal
O
Serial data output to the liquid crystal display driver
O
Chip select signal output to the liquid crystal display driver "L" active
O Serial data transfer clock signal output to the liquid crystal display driver
— Not used
— Ground terminal
I
Sub system clock input terminal (32.768 kHz)
O Sub system clock output terminal (32.768 kHz)
System reset signal input from the reset signal generator "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
O
Main system clock output terminal (16 MHz)
—
Ground terminal
I
Main system clock input terminal (16 MHz)
—
Power supply terminal (+3.3V)
I
Non-maskable interrupt input terminal Not used
I
Serial data transfer clock signal input from the RDS decoder Not used
I Subcode sync (S0+S1) detection signal input from the digital signal processor
I
AC off detection signal input from the reset signal generator "L": AC cut checked
O Tuner muting on/off control signal output to the tuner unit "H": muting on
O
PLL chip enable signal output to the tuner unit
O
PLL serial data output to the tuner unit
O
RFDC PWM signal output to the RF amplifier
I PLL serial data input from the tuner unit
O
PWM signal output to the RF amplifier
O
PLL serial data transfer clock signal output to the tuner unit
O
Focus servo drive PWM signal output to the RF amplifier
I/O Communication data transfer clock signal input/output terminal Not used
I/O
Communication data bus terminal Not used
—
Not used
I
Subcode Q data input from the digital signal processor
O Subcode Q data reading clock signal output to the digital signal processor
I
FM stereo detection signal input from the tuner unit "L": stereo
O
Serial data output to the digital signal processor
O Serial data latch pulse signal output to the digital signal processor
O Serial data transfer clock signal output to the digital signal processor
I
Head position detect switch input terminal
O
Clock (32.768 kHz) signal output terminal Not used
Line muting on/off control signal output to the recording/playback equalizer amplifier
O
"H": muting on
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y
Recording muting on/off control signal output to the recording/playback equalizer amplifier
O
"L": muting on
i
O
Recording bias on/off control signal output terminal "H": bias on
O
Recording/playback selection signal output terminal "L": playback, "H": recording
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Description
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