Table of Contents
Advertisement
SCHEMATIC DIAGRAM-18
MAIN (VIDEO:V) CIRCUIT
AUDIO
P5001
HEAD(R)
AUDIO
HEAD(L)
SP(L)
SP(R)
EP(L)
EP(R)
CYLINDER HEAD
J1
VEE0U97
P4001
FULL
ERASE
HEAD
P4002
AUDIO
ERASE
HEAD
AUDIO
HEAD
CONTROL
HEAD
AUDIO/CONTROL HEAD
S
BIAS [H]
IF
UNREG_6V
S
D_REC_H
A R
9
A COM
8
A L
7
SP L
C5001
0.01
6
SP COM
5
SP R
C5002
0.01
4
EP L
C5003
0.01
3
EP COM
2
EP R
C5004
0.01
1
FULL E
1
FULL E
2
R4071
15K
A E IN
1
GND
2
A HEAD[V]
3
A HEAD[R]
4
CTL HEAD[-]
5
CTL HEAD[+]
6
C2099
R2099
680P
6.8K
QR4082
UNR221300L
BIAS OSC
R4086
: +B SIGNAL LINE
: MAIN SIGNAL LINE
A_R
A
A_COM
A
A
A_L
C4065
1800P
S
CTL_HEAD [-]
CTL_HEAD [+]
S
EQQ7QF027Q
Q4081
B1AAGD000006
BIAS OSC
R4082
3.3K
C4084
1800P
C4083
C4085
R4083
6.3V47
0.068
2.2
R4087
2.2K
2.2K
L4081
G0C471KA0004
Q4084
2SB0710A0L
POWER SUPPLY
SP L
SP COM
SP R
EP L
EP COM
EP R
A HEAD[V]
R4081
8.2K
C4082
470P
T4081
4
3
2
6
1
C4081
0.022
QR4081
UNR211100L
D.REC (H:OFF)
R4015
20K
R4084
1K
Q4082
2SD114900L
BIAS OSC
R4085
1K
Q4083
2SD0601A0L
BIAS OSC
AUDIO_5V
A
Advertisement
Table of Contents
