JVC KD-LH2000 Service Manual page 44

KD-LH2000
QQ
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3.Pin function(2/2)
Pin No. Symbol I/O
51
IO4
I/O
52
VDD
53
IO5
I/O
54
IO6
I/O
55
IO7
I/O
56
VSSP
57
PDO
O
58
VCOI
59
VDDP
60
CKO
O
61
VDDX
62
XI
63
XO
O
64
VSSX
LP61L1024S-12-X (IC653) : SRAM
TE
L 13942296513
1. Pin layout
1
NC
2
A16
3
A14
4
A12
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
13
I/O1
14
I/O2
15
I/O3
16
Vss
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External SRAM data input/output 4 terminal
- Digital power supply (2.5V) terminal
External SRAM data input/output 5 terminal
External SRAM data input/output 6 terminal
External SRAM data input/output 7 terminal
VCO GND
-
PLL phase error detection signal output terminal
I VCO control voltage input terminal
VCO power supply
-
16.934 MHz clock output terminal
Power supply (2.5V) terminal for oscillator
-
Connection terminal for oscillator(input)
I
Connection terminal for oscillator(output)
GND for oscillator
-
32 V
DD
A15
31
CS2
30
29 WE
A13
28
A8
27
26 A9
25 A11
OE
24
23 A10
22 CS1
I/O8
21
I/O7
20
19 I/O6
I/O5
18
I/O4
17
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y
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Function
Q Q
3 6 7 1 3
2. Block diagram
V
DD
Vss
A0
DECODER
CORE
ARRAY
A16
CS2
CS1
CONTROL
DATA I/O
OE
WE
3. Pin function
SYMBOL DESCRIPTION
A0 - A16 Address Input
I/O1 - I/O8 Data Input/Output
CS1, CS2 Chip Select Inputs
WE Write Enable Input
OE Output Enable Input
V Power Supply
DD
Vss Ground
u163
NC No Connection
.
2 9 9 4 2 8
TC94A02F-005
1 5 0 5 8 2 9 9 4
I/O1
I/O8
m
co
9 9
2 8 9 9