Yamaha RX-V1065 Service Manual page 77

Av receiver/av amplifier
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Pin No. Function Name
I/O
1
RXOUT1
O
2
RX0
l
(pd)
5
3
RX1
I(pd)
4
RX2
l
(pd)
5
5
RX3
l
(pd)
5
6
DGND
7
DVDD
8
RX4
l
(pd)
5
9
RX5
l
(pd)
5
10
RX6
l
(pd)
5
11
DVDD
12
DGND
13
LPF
O
14
AVDD
15
AGND
16
RMCK
O
17
RBCK
O/I
18
DGND
19
DVDD
20
RLRCK
O/I
21
RDATA
O
22
SBCK
O
23
SLRCK
O
24
SDIN
l
5
25
DGND
26
DVDD
27
XMCK
O
28
XOUT
O
29
XIN
I
30
DVDD
31
DGND
32
MOUT
I/O
33
AUDIO
I/O
34
CKST
I/O
35
INT
I/O
36
RERR
O
37
DO
O
38
DI
l
5
39
CE
l
5
40
CL
l
5
41
XMODE
l
5
42
DGND
43
DVDD
44
GPIOO
O/I
45
GPI01
O/I
46
GPI02
O/I
47
GPI03
O/I
48
RXOUT2
O
* Input voltage: 1= -0.3 to 3.6V, Is =-0.3 to 5.5V
* Output voltage: 0= -0.3 to 3.6V
* Pins 2, 4, 5, 8, 9, 10, 24, 38, 39, 40, and 41 have an internal pull-down resistor (Pd).
Their level is fixed when they are unselected.
* Pins 32 and 33 are input pins for chip address setting when pin 41 is held at the low level.
* Pin 34 serves as the input pin for designating as the master or slave when pin 41 is held at the low level.
* Pin 35 serves as the input pin for configuring the I/O of pins 44 to 47 when pin 41 is held at the low level.
* The DVDD and AVDD pins must be held at the same level and turned on and off at the same timing to preclude latch-up conditions.
RX0-6 input S/PDIF through output pin 1
5V withstand voltage TIL input level compatible S/PDIF input pin (connected to GND when RX1 is
set)
Co-axial compatible S/PDIF input pin (supported demodulation sampling frequency of up to 96 kHz)
5V withstand voltage TIL input level compatible S/PDIF input pin (connected to GND when RX1 is
set)
5V withstand voltage TIL input level compatible S/PDIF input pin
Digital GND
Digital power supply (3.3V)
5V tolerable TIL input level compatible S/PDIF input pin
5V tolerable TIL input level compatible S/PDIF input pin
5V tolerable TIL input level compatible SIPDIF input pin
Digital power supply (3.3V)
Digital GND
PLL loop filter connection pin
Analog power supply (3.3V)
Analog GND
R system clock output pin (VCO, 512fs, XIN)
R system bit clock 1/0 pin (64fs)
Digital GND
Digital power supply (3.3V)
R system LR clock 1/0 pin (fs)
Serial audio data output pin
S system bit clock output pin (16fs, 32fs, 64fs, 128fs)
S system LR clock output pin (fs/4, fs/2, fs, 2fs)
External serial audio data input pin
Digital GND
Digital power supply (3.3V)
Oscillation amplifier clock output pin
Output pin connected to the resonator
External clock input pin. connected to the resonator (12.288 MHz or 24.576 MHz)
Digital power supply (3.3V)
Digital GND
Emphasis information II input fs monitor output II chip address setting input pin
Channel status bit 1 output II chip address setting input pin
Clock switching transition period signal output II master/slave setting input pin
Microcontroller interrupt signal output II pins 44-48 I/O setting input pin
PLL lock error and data error flag output pin
CCB microcontroller I/F, read data output pin (3-state)
CCB microcontroller I/F, write data input pin
CCB microcontroller I/F, chip enable input pin
CCB microcontroller I/F, clock input pin
System reset input pin
Digital GND
Digital power supply (3.3V)
General-purpose I/O pin II selector input pin (output referred to RMCK pin)
General-purpose I/O pin II selector input pin (output referred to RBCK pin)
General-purpose I/O pin II selector input pin (output referred to RLRCK pin)
General-purpose I/O pin II selector input pin (output referred to RDATA pin)
RX0-6 input S/PDIF through output pin 2
RX-V1065/HTR-6280/AX-V1065
Detail of Function
77

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