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P990+ Technical Service Manual
PIN CONFIGURATION
HFLB
1
XRAY
2
BOP
3
BSENS
4
BIN
5
BDRV
6
PGND
7
HDRV
8
TDA4841
XSEL
9
Vcc
10
EWDRV
11
VOUT2
12
VOUT1
13
VSYNC
14
HSYNC
15
CLBL
16
FUNCTIONAL DESCRIPTION
Horizontal sync separator and polarity correction
HSYNC (pin 15) is the input for horizontal
synchrodization signals, which can be DC-coupled
TTL signals (horizontal or composite sync) and AC-
coupled negative-going video sync signals. Video
syncs are clamped to 1.28V and sliced at 1.4V. This
results in a fixed absolute slicing level of 120mV
related to sync top.
For DC-coupled TTL signals the input clamping
current is limited. The slicing level for TTL signals is
1.4V.
The separated sync signal (either video or TTL) is
integrated on an internal capacitor to detect and
normalize the sync polarity.
Normalized horizontal sync pulses are used as input
Signals for the vertical sync integrator, the PLL1
phase detector and the frequency-locked loop.
Vertical sync integrator.
Normalized composite sync signals from HSYNC
are integrated on an internal capacitor in order to
extract vertical sync pulses. The integration time is
dependent on the horizontal oscillator reference
current at HREF (pin 28). The integrator output
directly triggers the vertical oscillator.
FOCUS
32
HSMOD
31
HPLL2
30
29
HCAP
HREF
28
HBUF
27
HPLL1
26
SGND
25
VCAP
24
VREF
23
VAGC
22
VSMOD
21
ASCOR
20
SDA
19
18
SCL
17
HUNLOCK
--22--
Vertical sync slicer and polarity correction
Vertical sync signals (TTL) applied to VSYNC (pin
14) are sliced at 1.4V. The output signal of the sync
slicer is integrated on an internal capacitor to
detect and normalize the sync polarity. The output
signals of vertical sync integrator and sync
normalizer are disjuncted before they are fed to the
vertical oscillator.
Video clamping vertical blanking generator
The video clamping vertical blanking signal at
CLBL (pin 16) is a two-level sandcastle pulse
which is especially suitable for video ICs such as
the TDA488x family, but also for direct
applications in video output stages.
The upper level is the video clamping pulse, which
is triggered by the horizontal sync pulse. Via I
bus Control either the leading or trailing edge can
be selected by setting control bit CLAMP. The
width of the video clamping pulse is determined
by an internal single-shot multivibrator.
The lower level of the sandcastle pulse is the
vertical blanking pulse, which is derived directly
from the internal oscillator waveform. It is started
by the vertical sync and stopped with the start of
the vertical scan. This results in optimum vertical
2
blanking. Via I
C-bus Control two different
vertical blanking times are accessible by control bit
VBLK.
Blanking will be activated continuously, if one of
the following conditions is true:
Soft start of horizontal and B+ drive (voltage at
HPLL2 (pin 30) pulled down externally or by I
bus)
PLL1 is unlocked while frequency-locked loop is in
search mode
No horizontal flyback pulses at HFLB (pin 1)
X-Ray protection is activated
Supply voltage at Vcc (pin 10) is low see Fig.22
2
Via I
C-bus Control horizontal unlock blanking
can be switched off by control bit BLKDIS while
vertical blanking is maintained.
Frequency-locked loop
The frequency locked loop can lock the horizontal
oscillator over a wide frequency range. This is
achieved by a combined search and PLL
operation. The frequency range is preset by two
external
resistors and the recommended maximum
f
ratio is
max
6.5
=
f
min
1
2
C-
2
C-
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