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Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
CLHT
LVCMOS/LVTTL Low-to-High Transition
Time, C
= 8pF, (Figure 5) (Note 8)
L
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
CHLT
LVCMOS/LVTTL High-to-Low Transition
Time, C
= 8pF, (Figure 5) (Note 8)
L
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
CLHT
LVCMOS/LVTTL Low-to-High Transition
Programmable
Time, C
= 8pF, (Figure 5) (Note 8)
L
adjustment
Register addr 28d/1ch,
bit [2] (RCLK)=1b (Default),
bit [1] (RXE) =1b (Default),
bit [0] (RXO) =1b (Default)
CHLT
LVCMOS/LVTTL High-to-Low Transition
Programmable
Time, C
= 8pF, (Figure 5) (Note 8)
L
adjustment
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
RCOP
RCLK OUT Period (Figures 11, 12) (Note 8)
RCOH
RCLK OUT High Time (Figures 11, 12)
RCOL
RCLK OUT Low Time (Figures 11, 12)
RSRC
RxOUT Setup to RCLK OUT (Figures 11, 12) (Notes 8, 9)
Register addr 29d/1dh [2:1]= 00b (Default)
RHRC
RxOUT Hold to RCLK OUT (Figures 11, 12) (Notes 8, 9)
Register addr 29d/1dh [2:1]= 00b (Default)
RSRC/RHRC
Register addr 29d/1dh [2:1] = 01b, (Figures 13, 14)
Programmable
(Notes 2, 10)
Adjustment
RSRC increased from default by 1UI
RHRC decreased from default by 1UI
Register addr 29d/1dh [2:1] = 10b, (Figures 13, 14)
(Notes 2, 10)
RSRC decreased from default by 1UI
RHRC increased from default by 1UI
Register addr 29d/1dh [2:1] = 11b, (Figures 13, 14)
(Notes 2, 10)
RSRC increased from default by 2UI
RHRC decreased from default by 2UI
RPLLS
Receiver Phase Lock Loop Set (Figure 6)
RPDD
Receiver Powerdown Delay (Figure 7)
RPDL
Receiver Propagation Delay — Latency (Figure 8)
RITOL
Receiver Input Tolerance
(Figures 10, 16) (Notes 8, 10)
Note 8: Specification is guaranteed by characterization.
Note 9: A Clock Unit Symbol (T) is defined as 1/ (Line rate of RCLK). E.g. For Line rate of RCLK at 85MHz, 1 T = 11.76ns
Note 10: A Unit Interval (UI) is defined as 1/7th of an ideal clock period (RCLK/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns
Parameter
Condition/
Min
Reference
Rx clock out
Rx data out
Rx clock out
Rx data out
Rx clock out
Rx data out
Rx clock out
Rx data out
8–135 MHz
7.4
Rx clock out
0.4T
Rx clock out
0.4T
2.60
3.60
= 1.25V,
V
CM
V
= 350mV
ID
5
Typ
Max
Units
1.45
2.10
ns
2.40
3.50
ns
1.35
2.20
ns
2.40
3.60
ns
2.45
ns
3.40
ns
2.35
ns
3.40
ns
T
125
ns
0.5T
0.6T
ns
0.5T
0.6T
ns
0.5T
ns
0.5T
ns
+1UI /
ns
-1UI
-1UI /
ns
+1UI
+2UI /
ns
-2UI
10
ms
100
ns
4*RCLK
ns
0.25
UI
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