Table of Contents
Advertisement
Quick Links
DS90C3202
3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver
General Description
The DS90C3202 is a 3.3V single/dual FPD-Link 10-bit color
receiver is designed to be used in Liquid Crystal Display
TVs, LCD Monitors, Digital TVs, and Plasma Display Panel
TVs. The DS90C3202 is designed to interface between the
digital video processor and the display device using the
low-power, low-EMI LVDS (Low Voltage Differential Signal-
ing) interface. The DS90C3202 converts up to ten LVDS
data streams back into 70 bits of parallel LVCMOS/LVTTL
data. The receiver can be programmed with rising edge or
falling edge clock. Optional wo-wire serial programming al-
lows fine tuning in development and production environ-
ments. With an input clock at 135 MHz, the maximum trans-
mission rate of each LVDS line is 945 Mbps, for an
aggregate throughput rate of 9.45 Gbps (945 Mbytes/s). This
allows the dual 10-bit LVDS Receiver to support resolutions
up to HDTV.
Block Diagram
© 2006 National Semiconductor Corporation
Features
n Up to 9.45 Gbit/s data throughput
n 8 MHz to 135 MHz input clock support
n Supports up to QXGA panel resolutions
n Supports HDTV panel resolutions and frame rates up to
1920 x 1080p
n LVDS 30-bit, 24-bit or 18-bit color data inputs
n Supports single pixel and dual pixel interfaces
n Supports spread spectrum clocking
n Two-wire serial communication interface
n Programmable clock edge and control strobe select
n Power down mode
n +3.3V supply voltage
n 128-pin TQFP Package
n Compliant to TIA/EIA-644-A-2001 LVDS Standard
FIGURE 1. Receiver Block Diagram
DS201471
September 2006
20147101
www.national.com
Advertisement
Table of Contents
Summary of Contents for National Semiconductor DS90C3202
-
Page 1: General Description
DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver General Description The DS90C3202 is a 3.3V single/dual FPD-Link 10-bit color receiver is designed to be used in Liquid Crystal Display TVs, LCD Monitors, Digital TVs, and Plasma Display Panel TVs. -
Page 2: Typical Application Diagram
Typical Application Diagram Functional Description The DS90C3201 and DS90C3202 are a dual 10-bit color Transmitter and Receiver FPD-Link chipset designed to transmit data at clocks speeds from 8 to 135 MHz. DS90C3201 and DS90C3202 are designed to interface be- tween the digital video processor and the display using a LVDS interface. -
Page 3: Absolute Maximum Ratings
Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V LVCMOS/LVTTL Input Voltage −0.3V to (V LVCMOS/LVTTL Output Voltage −0.3V to (V LVDS Receiver Input Voltage −0.3V to (V Junction Temperature Storage Temperature... - Page 4 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter RECEIVER SUPPLY CURRENT ICCRW Receiver Supply Current Worst Case (Figures 2, 4) ICCRG Receiver Supply Current Incremental Test Pattern (Figures 3, 4) ICCRZ Receiver Supply Current Power Down Note 1: “Absolute Maximum Ratings”...
- Page 5 Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter CLHT LVCMOS/LVTTL Low-to-High Transition Time, C = 8pF, (Figure 5) (Note 8) Register addr 28d/1ch, bit [2] (RCLK)=0b (Default), bit [1] (RXE) =0b (Default), bit [0] (RXO) =0b (Default) CHLT LVCMOS/LVTTL High-to-Low Transition Time, C...
- Page 6 Two-Wire Serial Communication Interface Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter S2CLK Clock Frequency SC:LOW Clock Low Period SC:HIGH Clock High Period SCD:TR S2CLK and S2DAT Rise Time SCD:TF S2CLK and S2DAT Fall Time SU:STA Start Condition Setup Time HD:STA Start Condition Hold Time...
- Page 7 AC Timing Diagrams (Continued) 20147103 FIGURE 2. “Worst Case” Test Pattern 20147104 FIGURE 3. Incremental Test Pattern 20147105 FIGURE 4. Typical and Max ICC with Worse Case and Incremental Pattern 20147106 FIGURE 5. LVCMOS/LVTTL Output Load and Transition Times www.national.com...
- Page 8 AC Timing Diagrams (Continued) 20147107 FIGURE 6. Receiver Phase Lock Loop Wake-up Time 20147108 FIGURE 7. Powerdown Delay 20147109 FIGURE 8. Receiver Propagation Delay www.national.com...
- Page 9 AC Timing Diagrams (Continued) 20147110 FIGURE 9. RFB: LVTTL Level Programmable Strobe Select 20147111 RITOL ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 11) + ISI (Inter-symbol interference) (Note 12) Cable Skew — typically 10 ps–40 ps per foot, media dependent Please see National’s AN-1217 for more details.
- Page 10 AC Timing Diagrams (Continued) 20147113 RegisterAddress 29d/1dh bit [2:1] = 00b FIGURE 12. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Enabled 20147114 FIGURE 13. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Disabled www.national.com...
- Page 11 AC Timing Diagrams (Continued) 20147115 FIGURE 14. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Enabled www.national.com...
- Page 12 AC Timing Diagrams (Continued) 20147116 FIGURE 15. LVDS Input Mapping www.national.com...
- Page 13 AC Timing Diagrams (Continued) 20147117 FIGURE 16. Receiver RITOL Min and Max www.national.com...
-
Page 14: Pin Diagram
Pin Diagram DS90C3202 Receiver 20147118 www.national.com... - Page 15 DS90C3202 Pin Descriptions Pin No. Pin Name S2DAT S2CLK VDDP1 VSSP1 VSSP0 VDDP0 PWDNB RXEE0 RXEE1 RXEE2 RXEE3 RXEE4 RXEE5 RXEE6 VSS0 VDD0 RXED0 RXED1 RXED2 RXED3 RXED4 RXED5 RXED6 VSSR0 VDDR0 RXEC0 RXEC1 RXEC2 RXEC3 RXEC4 RXEC5 VSS1 VDD1...
- Page 16 DS90C3202 Pin Descriptions Pin No. Pin Name VDD2 RXEA0 RXEA1 RXEA2 RXEA3 RXEA4 RXEA5 RXEA6 VSS3 VDD3 RXOE0 RXOE1 RXOE2 RXOE3 RXOE4 RXOE5 RXOE6 RXOD0 VSS4 VDD4 RXOD1 RXOD2 RXOD3 RXOD4 RXOD5 RXOD6 RXOC0 RXOC1 RXOC2 RXOC3 RXOC4 RXOC5 RXOC6...
- Page 17 DS90C3202 Pin Descriptions Pin No. Pin Name RXOA4 RXOA5 RXOA6 VDD5 VSS5 RESRVD MODE1 VSSL VDDL RXOA- RXOA+ RXOB- RXOB+ RXOC- RXOC+ RXOD- RXOD+ RXOE- RXOE+ VSSL VSSL VDDL VDDL RCLKIN- RCLKIN+ RXEA- RXEA+ RXEB- RXEB+ RXEC- RXEC+ RXED- RXED+...
- Page 18 Two-Wire Serial Communication Interface Description The DS90C3202 operates as a slave on the Serial Bus, so the S2CLK line is an input (no clock is generated by the DS90C3202) S2DAT line DS90C3202 has a fixed 7bit slave address. The address is not user configurable in anyway.
- Page 19 DS90C3202 Two-Wire Serial Interface Register Table Address RESET 0d/0h PWDN 1d/1h PWDN 2d/2h PWDN 3d/3h PWDN 4d/4h PWDN 5d/5h PWDN 6d/6h PWDN 7d/7h PWDN 8d/8h PWDN 9d/9h PWDN 10d/ah PWDN 11d/bh PWDN 20d/14h None 21d/15h None 22d/16h None 23d/17h None...
- Page 20 DS90C3202 Two-Wire Serial Interface Register Table Address RESET 26d/1ah None 27d/1bh None 28d/1ch None 29d/1dh None www.national.com Bit # Description Reserved [6:4] LVDS input skew control for RXE channel B, 000 (default) applies to no delay added, ONE buffer delay per step adjustment towards Thold improvements...
- Page 21 DS90C3202 Two-Wire Serial Interface Register Table Address RESET 30d/1eh None 31d/1fh None Note 13: Registers with RESET designated with “None” requires device to be power cycled to reset register values to their default state. Bit # Description [7:5] Reserved I/O disable control for RXE channel A,...
-
Page 22: Physical Dimensions
Physical Dimensions inches (millimeters) unless otherwise noted National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com.