National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ User Manual
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National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ User Manual

National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ User Manual

Low-cost multifunction i/o board for isa
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Lab-PC+

User Manual

Low-Cost Multifunction I/O Board for ISA
June 1996 Edition
Part Number 320502B-01
© Copyright 1992, 1996 National Instruments Corporation.
All Rights Reserved.

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Summary of Contents for National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+

  • Page 1: User Manual

    Lab-PC+ User Manual Low-Cost Multifunction I/O Board for ISA June 1996 Edition Part Number 320502B-01 © Copyright 1992, 1996 National Instruments Corporation. All Rights Reserved.
  • Page 2 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, TX 78730-5039 (512) 794-0100 Technical support fax: (512) 794-5678 Branch Offices: Australia 03 9 879 9422, Austria 0662 45 79 90 0, Belgium 02 757 00 20, Canada (Ontario) 519 622 9310, Canada (Québec) 514 694 8521, Denmark 45 76 26 00, Finland 90 527 2321, France 1 48 14 24 24,...

  • Page 3: Warranty

    Any action against National Instruments must be brought within one year after the cause of action accrues. National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover damages, defects, malfunctions, or service failures caused by owner's failure to follow the National Instruments installation, operation, or maintenance instructions;...
  • Page 4 Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used.

  • Page 5: Table Of Contents

    Contents About This Manual ... xi Organization of the Lab-PC+ User Manual ... xi Conventions Used in This Manual ... xii National Instruments Documentation ... xiii Customer Communication ... xiii Chapter 1 Introduction ... 1-1 About the Lab-PC+ ... 1-1 What You Need to Get Started ...
  • Page 6 Data Acquisition Timing Circuitry ... 4-5 Single-Channel Data Acquisition... 4-6 Multiple-Channel (Scanned) Data Acquisition ... 4-6 Data Acquisition Rates... 4-7 Analog Output Circuitry ... 4-9 Digital I/O Circuitry ... 4-10 Timing I/O Circuitry ... 4-11 Lab-PC+ User Manual © National Instruments Corporation...
  • Page 7 OKI 82C55A Data Sheet Appendix D Register Map and Descriptions Appendix E Register-Level Programming Appendix F Customer Communication Glossary ... Glossary-1 Index ... Index-1 © National Instruments Corporation ... C-1 ... D-1 ... E-1 ... F-1 Contents Lab-PC+ User Manual...
  • Page 8 Figure 3-13. EXTUPDATE* Signal Timing for Updating DAC Output ... 3-24 Figure 3-14. EXTUPDATE* Signal Timing for Generating Interrupts ... 3-24 Figure 3-15. Event-Counting Application with External Switch Gating... 3-25 Figure 3-16. Frequency Measurement Application ... 3-26 Figure 3-17. General-Purpose Timing Signals ... 3-27 Figure 4-1.
  • Page 9 Table E-4. Analog Output Voltage Versus Digital Code (Bipolar Mode, Two’s Complement Coding) ... E-22 Table E-5. Mode 0 I/O Configurations ... E-26 Table E-6. Port C Set/Reset Control Words ... E-33 © National Instruments Corporation Tables Contents Lab-PC+ User Manual...

  • Page 10: About This Manual

    Appendix E, Register-Level Programming, contains important information about programming the Lab-PC+. • Appendix F, Customer Communication, contains forms you can use to request help from National Instruments or to comment on our products and manuals. © National Instruments Corporation Lab-PC+ User Manual...

  • Page 11: Conventions Used In This Manual

    Paths are denoted using backslashes (\) to separate drive names, directories, folders, and files. Square brackets enclose optional items (for example, [response]). The Glossary lists abbreviations, acronyms, metric prefixes, mnemonics, symbols, and terms. Lab-PC+ User Manual © National Instruments Corporation...

  • Page 12: National Instruments Documentation

    Customer Communication National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them.

  • Page 13: Chapter 1 Introduction

    To set up and use your Lab-PC+ board, you will need the following: Lab-PC+ board Lab-PC+ User Manual One of the following software packages and documentation: NI-DAQ for PC compatibles LabVIEW LabWindows/CVI Your computer © National Instruments Corporation Lab-PC+ User Manual...

  • Page 14: Software Programming Choices

    NI-DAQ Driver Software The NI-DAQ driver software is included at no charge with all National Instruments DAQ hardware. NI-DAQ is not packaged with signal conditioning or accessory products. NI-DAQ has an extensive library of functions that you can call from your application programming environment.

  • Page 15: Register-Level Programming

    Series DAQ and SCXI hardware, with NI-DAQ software for PC compatibles. Register-Level Programming The final option for programming any National Instruments DAQ hardware is to write register- level software. Writing register-level programming software can be very time-consuming and inefficient and is not recommended for most users.

  • Page 16: Optional Equipment

    • Remove the board from the package and inspect the board for loose components or any other sign of damage. Notify National Instruments if the board appears damaged in any way. Do not install a damaged board into your computer.

  • Page 17: Chapter 2 Configuration And Installation

    The Lab-PC+ contains six jumpers and one DIP switch to configure the PC bus interface and analog I/O settings. The DIP switch is used to set the base I/O address. Two jumpers are used as interrupt channel and DMA selectors. The remaining four jumpers are used to change the analog input and analog output circuitry.

  • Page 18: Figure 2-1. Parts Locator Diagram

    Configuration and Installation Assembly Number Spare Fuse Lab-PC+ User Manual Serial Number Fuse Figure 2-1. Parts Locator Diagram Chapter 2 Product Name © National Instruments Corporation...

  • Page 19: Base I/O Address Selection

    Figure 2-1). The switches are set at the factory for the base I/O address hex 260. This factory setting is used as the default base I/O address value by National Instruments software packages for use with the Lab-PC+. The Lab-PC+ uses the base I/O address space hex 260 through 27F with the factory setting.

  • Page 20: Figure 2-2. Example Base I/O Address Switch Settings

    Lab-PC+ register. To change the base I/O address, remove the plastic cover on U1; press each switch to the desired position; check each switch to make sure the switch is pressed down all the way; and replace the plastic cover. Record the new Lab-PC+ base I/O address in Appendix F, Customer Communication, for use when configuring the Lab-PC+ software.

  • Page 21: Table 2-2. Switch Settings With Corresponding Base I/O Address And Base I/O Address Space

    Chapter 2 Table 2-2. Switch Settings with Corresponding Base I/O Address Switch Setting A9 A8 A7 A6 A5 Note:Base I/O address values hex 000 through 0FF are reserved for system use. Base I/O address values hex 100 through 3FF are available on the I/O channel.

  • Page 22: Dma Channel Selection

    W6 in the position shown in Figure 2-4. Lab-PC+ User Manual Acknowledge DACK1 DACK2 DACK3 DACK* • • • • • • • • • • • • • • Chapter 2 Request DRQ1 DRQ2 DRQ3 • • © National Instruments Corporation...

  • Page 23: Interrupt Selection

    5. Figure 2-5 shows the default interrupt jumper setting IRQ5. To change to another line, remove the jumper from IRQ5 and place it on the new pins. Figure 2-5. Interrupt Jumper Setting IRQ5 (Factory Setting) © National Instruments Corporation DACK* •...

  • Page 24: Analog I/O Configuration

    5 V output range Table 2-4 lists all the available analog I/O jumper configurations for the Lab-PC+ with the factory settings noted. Lab-PC+ User Manual • • • • • • • • • • • • © National Instruments Corporation Chapter 2...

  • Page 25: Analog Output Configuration

    You can select the bipolar ( 5 V) output configuration for either analog output channel by setting the following jumpers: Analog Output Channel 0 Analog Output Channel 1 This configuration is shown in Figure 2-7. Figure 2-7. Bipolar Output Jumper Configuration (Factory Setting) © National Instruments Corporation Configuration • • • •...

  • Page 26: Unipolar Output Selection

    (NRSE) input, and differential (DIFF) input. The single-ended input configurations use eight channels. The DIFF input configuration uses four channels. These configurations are described in Table 2-5. Lab-PC+ User Manual • • • • • • Channel 0 Channel 1 2-10 Chapter 2 © National Instruments Corporation...

  • Page 27: Diff Input (Four Channels)

    Register 4 bit description in Appendix D, Register Map and Descriptions. You must also set the following jumper. Jumper is in stand-by position, and negative input of instrumentation amplifier is tied to multiplexer output. © National Instruments Corporation Configuration and Installation Description /D bit as described in the Command...

  • Page 28: Rse Input (Eight Channels, Factory Setting)

    Considerations in using the RSE configuration are discussed in Chapter 3, Signal Connections. Note that in this mode, the return path of the signal is analog ground, available at the connector through pin AISENSE/AIGND. Lab-PC+ User Manual • NRSE/DIFF • NRSE/DIFF 2-12 © National Instruments Corporation Chapter 2...

  • Page 29: Nrse Input (Eight Channels)

    Bipolar Input Selection You can select the bipolar ( 5 V) input configuration by setting the following jumper: Analog Input This configuration is shown in Figure 2-12. © National Instruments Corporation • NRSE/DIFF 2-13 Configuration and Installation...

  • Page 30: Unipolar Input Selection

    This configuration is shown in Figure 2-13. Figure 2-13. Unipolar Input Jumper Configuration Note: If you are using a software package such as NI-DAQ or LabWindows/CVI, you may need to reconfigure your software to reflect any changes in jumper or switch settings. Lab-PC+ User Manual •...

  • Page 31: Hardware Installation

    If you are using LabVIEW, the software installation instructions are in your LabVIEW release notes. If you are using LabWindows/CVI, the software installation instructions are in your LabWindows/CVI release notes. If you are a register-level programmer, refer to Appendix E, Register-Level Programming. © National Instruments Corporation 2-15 Lab-PC+ User Manual...

  • Page 32: Chapter 3 Signal Connections

    Lab-PC+ may result in damage to the Lab-PC+ board and to the computer. This includes connecting any power signals to ground and vice versa. National Instruments is connections. © National Instruments Corporation liable for any damages resulting from any such signal Lab-PC+ User Manual...

  • Page 33: Signal Connection Descriptions

    35 36 37 38 EXTTRIG 39 40 EXTCONV* EXTUPDA TE* OUTB0 41 42 GA TB0 COUTB1 43 44 GA TB1 CCLKB1 45 46 OUTB2 GA TB2 47 48 CLKB2 +5 V 49 50 DGND Chapter 3 © National Instruments Corporation...
  • Page 34 OUTB2 GATB2 CLKB2 DGND *Indicates that the signal is active low. © National Instruments Corporation Description Analog input Channels 0 through 7 (single-ended). Analog input ground in RSE mode, AISENSE in NRSE mode. Bi-directional. Voltage output signal for analog output Channel 0.

  • Page 35: Analog Input Signal Connections

    Exceeding the input signal range results in distorted input signals. Exceeding the maximum input voltage rating may cause damage to the Lab-PC+ board and to the computer. National Instruments is such signal connections. Connection of analog input signals to the Lab-PC+ depends on the configuration of the Lab-PC+ analog input circuitry and the type of input signal source.

  • Page 36: Types Of Signal Sources

    The ground reference of a floating signal must be tied to the Lab-PC+ analog input ground in order to establish a local or onboard reference for the signal. Otherwise, © National Instruments Corporation Instrumentation Amplifier...

  • Page 37: Ground-Referenced Signal Sources

    Lab-PC+ User Manual and Floating Signal Sources Recommended Input Configuration DIFF NRSE DIFF with bias resistors Chapter 3 © National Instruments Corporation...

  • Page 38: Differential Connections For Grounded Signal Sources

    Figure 3-3 shows how to connect a ground-referenced signal source to a Lab-PC+ board configured for DIFF input. Configuration instructions are included under Analog Input Configuration in Chapter 2, Configuration and Installation. © National Instruments Corporation Signal Connections Lab-PC+ User Manual...

  • Page 39: Differential Connections For Floating Signal Sources

    Chapter 2, Configuration and Installation. Lab-PC+ User Manual ACH 0 ACH 2 ACH 4 ACH 6 ACH 1 ACH 3 ACH 5 ACH 7 (not connected) AISENSE/AIGND AGND Lab-PC+ Board in DIFF Configuration Chapter 3 Measured V oltage © National Instruments Corporation...

  • Page 40: Figure 3-4. Differential Input Connections For Floating Sources

    If the input signal is DC-coupled, then only the resistor connecting the negative signal input to ground is needed. This connection does not lower the input impedance of the analog input channel. © National Instruments Corporation ACH 0 ACH 2...

  • Page 41: Single-Ended Connection Considerations

    The Lab-PC+ analog input circuitry must be configured for RSE input to make these types of connections. Configuration instructions are included under Analog Input Configuration in Chapter 2, Configuration and Installation. Lab-PC+ User Manual 3-10 © National Instruments Corporation...

  • Page 42: Single-Ended Connections For Grounded Signal Sources (Nrse Configuration)

    Figure 3-6 shows how to connect a grounded signal source to a Lab-PC+ board configured in the NRSE configuration. Configuration instructions are included under Analog Input Configuration in Chapter 2, Configuration and Installation. © National Instruments Corporation ACH 0 ACH 1...

  • Page 43: Common-Mode Signal Rejection Considerations

    Analog Output Channel 0. DAC1 OUT is the voltage output signal for Analog Output Channel 1. Lab-PC+ User Manual ACH 0 ACH 1 ACH 2 ACH 7 AISENSE/AIGND AGND Lab-PC+ Board in NRSE Input Configuration 3-12 Chapter 3 Measured V oltage © National Instruments Corporation...

  • Page 44: Digital I/O Signal Connections

    Pins 14 through 21 are connected to the digital lines PA<0..7> for digital I/O Port A. Pins 22 through 29 are connected to the digital lines PB<0..7> for digital I/O Port B. Pins 30 through 37 © National Instruments Corporation Bipolar input: 5 V...
  • Page 45 Figure 3-8 illustrates signal connections for three typical digital I/O applications. Lab-PC+ User Manual Minimum -0.3 V 2.2 V 3.7 V 2.5 mA = 1.7 V) 3-14 Chapter 3 Maximum 0.8 V 5.3 V 0.4 V 4.0 mA © National Instruments Corporation...

  • Page 46: Port C Pin Connections

    In Figure 3-8, Port A is configured for digital output, and Ports B and C are configured for digital input. Digital input applications include receiving TTL signals and sensing external device states such as the switch in Figure 3-8. Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 3-8.

  • Page 47: Timing Specifications

    INTR A ACK A * INTR A ACK A * IBF A STB A * INTR A 3-16 Chapter 3 Group B STB B * IBFB B INTR B ACK B * OBF B * INTR B © National Instruments Corporation...
  • Page 48 PC I/O channel. DATA Bidirectional Data lines at the specified port–This signal indicates when the data on the data lines at a specified port is or should be available. © National Instruments Corporation 3-17 Signal Connections Lab-PC+ User Manual...

  • Page 49: Mode 1 Input Timing

    Data after STB* = 1 RD* = 0 to INTR = 0 RD* = 1 to IBF = 0 All timing values are in nanoseconds. Lab-PC+ User Manual Minimum – – – – 3-18 © National Instruments Corporation Chapter 3 Maximum – – –...

  • Page 50: Mode 1 Output Timing

    WR* = 1 to output WR* = 1 to OBF* = 0 ACK* = 0 to OBF* = 1 ACK* pulse width ACK* = 1 to INTR = 1 All timing values are in nanoseconds. © National Instruments Corporation Minimum – – – –...

  • Page 51: Mode 2 Bidirectional Timing

    ACK* = 1 to output float RD* = 1 to IBF = 0 All timing values are in nanoseconds. Lab-PC+ User Manual Minimum – – – – – 3-20 Chapter 3 Maximum – – – – © National Instruments Corporation...

  • Page 52: Timing Connections

    EXTCONV*, following the rising edge on the EXTTRIG line. Further transitions on the EXTTRIG line have no effect until a new data acquisition sequence is established. Figures 3-10 © National Instruments Corporation t w 250 nsec minimum A/D Conversion starts within 125 nsec from this point.

  • Page 53: Figure 3-10. Posttrigger Data Acquisition Timing Case 1

    EXTTRIG V IL EXTCONV* CONVERT Sample Counter Figure 3-11. Posttrigger Data Acquisition Timing Case 2 Lab-PC+ User Manual t w 50 nsec minimum t w 50 nsec minimum t d 50 nsec minimum 3-22 Chapter 3 © National Instruments Corporation...

  • Page 54: Figure 3-12. Pretrigger Data Acquisition Timing

    Notice that the DACs are updated by a low level on the EXTUPDATE* line. Any writes to the DAC Data Registers while EXTUPDATE* is low therefore result in immediate update of the DAC output voltages. © National Instruments Corporation t w 50 nsec minimum 3-23...

  • Page 55: General-Purpose Timing Signal Connections And General-Purpose Counter/Timing Signals

    8253(B) counters. The 8253 Counter/Timers can be used for general-purpose applications such as pulse and square wave generation; event counting; and pulse-width, time-lapse, and frequency Lab-PC+ User Manual t ext t ext Minimum 50 nsec 3-24 © National Instruments Corporation Chapter 3...

  • Page 56: Figure 3-15. Event-Counting Application With External Switch Gating

    8253 CLK inputs. The counter value can then be read to determine the number of edges that have occurred. Counter operation can be gated on and off during event counting. Figure 3-15 shows connections for a typical event-counting operation where a switch is used to gate the counter on and off.

  • Page 57: Figure 3-16. Frequency Measurement Application

    Figure 3-17 shows the timing requirements for the GATE and CLK input signals and the timing specifications for the OUT output signals of the 8253. Lab-PC+ User Manual +5 V 4.7 k GATE Counter DGND Lab-PC Board 3-26 © National Instruments Corporation Chapter 3...

  • Page 58: Figure 3-17. General-Purpose Timing Signals

    Figure 3-17. General-Purpose Timing Signals © National Instruments Corporation 2.2 V minimum 0.8 V maximum 10 A maximum 3.7 V minimum 0.45 V maximum -1 mA maximum...

  • Page 59: Cabling

    The GATE and OUT signals in Figure 3-17 are referenced to the rising edge of the CLK signal. Cabling National Instruments currently offers a cable termination accessory, the CB-50, for use with the Lab-PC+ board. This kit includes a terminated, 50-conductor, flat ribbon cable and a connector block.

  • Page 60: Chapter 4 Theory Of Operation

    The block diagram in Figure 4-1 shows a functional overview of the Lab-PC+ board. Data/ Address PC I/O Channel Interface Control Signals 1-MHz Timebase 10 MHz Oscillator Figure 4-1. Lab-PC+ Block Diagram © National Instruments Corporation 12-Bit FIFO 8253 8255A Ctr/Timer Digital Group A Interface 2 MHz Timebase Input Gain...

  • Page 61: Pc I/O Channel Interface Circuitry

    The PC I/O channel consists of an address bus, a data bus, a DMA arbitration bus, interrupt lines, and several control and support signals. The components making up the Lab-PC+ PC I/O channel interface circuitry are shown in Figure 4-2. Lab-PC+ User Manual © National Instruments Corporation Chapter 4...

  • Page 62: Figure 4-2. Pc I/O Interface Circuitry Block Diagram

    • When an A/D conversion is available to be read from FIFO • When either an OVERFLOW or an OVERRUN error occurs • When DMA terminal count pulse is received © National Instruments Corporation Address Decoder Timing Interface Data Buffers...

  • Page 63: Analog Input And Data Acquisition Circuitry

    Figure 4-3. Analog Input and Data Acquisition Circuitry Block Diagram Lab-PC+ User Manual Pro- Sample- grammable and-Hold Gain Amp GAIN0 GAIN1 GAIN2 Counter Data MUX CTR CLK Acquisition Timing External Trigger Chapter 4 Data Data FIFO CONV AVAIL Data Command Registers ADC WR Counter/Timer Signals © National Instruments Corporation...

  • Page 64: Analog Input Circuitry

    (the time between successive A/D conversions) carefully timed. The data acquisition timing circuitry consists of various clocks and timing signals that perform this timing. The Lab-PC+ board can perform both single-channel data acquisition and multiple-channel © National Instruments Corporation Lab-PC+ User Manual...

  • Page 65: Single-Channel Data Acquisition

    Chapter 4 (scanned) data acquisition in two modes–continuous and interval. The Lab-PC+ uses a counter to switch between analog input channels automatically during scanned data acquisition. Data acquisition timing consists of signals that initiate a data acquisition operation, initiate individual A/D conversions, gate the data acquisition operation, and generate scanning clocks.

  • Page 66: Data Acquisition Rates

    Table 4-2 ensures 12-bit accuracy. Table 4-1. Analog Input Settling Time Versus Gain Gain Setting 2, 5, 10, 20, 50 © National Instruments Corporation Settling Time Recommended 12 s 16 s typical, 18 s maximum...

  • Page 67: Table 4-2. Lab-Pc+ Maximum Recommended Data Acquisition Rates

    0 mV to 999.756 mV 0 mV to 499.877 mV 0 mV to 199.951 mV 0 mV to 99.975 mV Chapter 4 Rate 83.3 ksamples/s 71.4 ksamples/s* 83.3 ksamples/s 62.5 ksamples/s typical, 55.5 ksamples/s worst case 20.0 ksamples/s © National Instruments Corporation...

  • Page 68: Analog Output Circuitry

    If this bit is cleared, the DAC output voltage is updated as soon as the corresponding DAC Data Register is written to. If the LDAC bit is set, the DAC output voltage does not change until a falling edge is detected either from Counter A2 or from EXTUPDATE*. © National Instruments Corporation 2SDAC0 Coding...

  • Page 69: Digital I/O Circuitry

    I/O, or bidirectional bus. The programming of the digital I/O circuitry is covered in Appendix E, Register-Level Programming. DATA<0..7> DIO RD/WR Interrupt Control Figure 4-5. Digital I/O Circuitry Block Diagram Lab-PC+ User Manual 8255A Programmable Peripheral Interface 4-10 © National Instruments Corporation Chapter 4 PA<0..7> PB<0..7> PC<0..7>...

  • Page 70: Timing I/O Circuitry

    I/O functions. One of these is used internally for data acquisition timing, and the other is available for general use. Figure 4-6 shows a block diagram of both groups of timing I/O circuitry (counter groups A and B). © National Instruments Corporation 4-11 Lab-PC+ User Manual...

  • Page 71: Figure 4-6. Timing I/O Circuitry Block Diagram

    Timebase Extension/ General Purpose Counter CLKB0 8253 Counter/Timer Group B 2 MHz Source A/D Conversion Logic +5 V D/A Conversion Timing 4-12 Chapter 4 GATEB2 CLKB2 OUTB2 GATEB1 CCLKB1 CLKA0 OUTB0 GATEB0 COUTB1 EXTCONV* EXTTRIG EXTUPDATE* © National Instruments Corporation...

  • Page 72: Figure 4-7. Two-Channel Interval-Scanning Timing

    Counter is programmed to count three samples, wait for the duration of the scan interval, count three samples, and so on. The acquisition operation ends when the sample counter (Counter A1) decrements to 0. © National Instruments Corporation Scan Interval...

  • Page 73: Figure 4-8. Single-Channel Interval Timing

    Each counter has a CLK input pin, a GATE input pin, and an output pin labeled OUT. The 8253 counters are numbered 0 through 2, and their GATE, CLK, and OUT pins are labeled GATE N, CLK N, and OUT N, where N is the counter number. Lab-PC+ User Manual 4-14 © National Instruments Corporation...

  • Page 74: Chapter 5 Calibration

    Accuracy Range Resolution For analog output calibration, you need a voltmeter with these features: Accuracy Range Resolution © National Instruments Corporation 0.001% standard 0.003% sufficient Greater than 10 V 100 V in 10 V range (5 digits) 0.001% standard 0.003% sufficient...

  • Page 75: Calibration Trimpots

    R3 – Gain trim, analog output Channel 1 • R4 – Offset trim, analog output Channel 1 • R1 – Gain trim, analog output Channel 0 • R2 – Offset trim, analog output Channel 0 Lab-PC+ User Manual Chapter 5 © National Instruments Corporation...

  • Page 76: Analog Input Calibration

    ADC returns readings that flicker between its most positive count and the most positive count minus 1. The voltages corresponding to V and 1 LSB are given in Table 5-1. © National Instruments Corporation -1.5 LSB to the Calibration Lab-PC+ User Manual...

  • Page 77: Board Configuration

    1, followed by recording the average reading at all other gains. These readings can be used Lab-PC+ User Manual , which is the most negative voltage that the ADC can read, -5 V +4.99756 V +9.99756 V Chapter 5 1 LSB 0.5 LSB 2.44 mV 1.22 mV 2.44 mV 1.22 mV © National Instruments Corporation...

  • Page 78: Unipolar Input Calibration Procedure

    Adjust trimpot R6 until the readings flicker between 0 and 1. Care must be taken to avoid setting the potentiometer too low in the unipolar mode. If the potentiometer is set too low, the ADC then simply outputs 0 because its input is below the lower limit. © National Instruments Corporation - 1.5 LSB. Calibration...

  • Page 79: Analog Output Calibration

    Bipolar Output Calibration Procedure If your board is configured for bipolar output, which provides an output range of -5 to +5 V, then complete the following procedures in the order given. Lab-PC+ User Manual - 1.5 LSB. © National Instruments Corporation Chapter 5...
  • Page 80 Set the analog output channel to +4.99756 V by writing 2,047 to the DAC. c. Adjust trimpot R3 until the output voltage read is +4.99756 V. © National Instruments Corporation 0.5 LSB. For bipolar output, 0.5 LSB. For bipolar output,...

  • Page 81: Unipolar Output Calibration Procedure

    Set the analog output channel to +9.99756 V by writing 4,095 to the DAC. c. Adjust trimpot R3 until the output voltage read is +9.99756 V. Lab-PC+ User Manual 0.5 LSB. For unipolar © National Instruments Corporation Chapter 5...

  • Page 82: Appendix A Specifications

    After calibration ... Adjustable to 0% Before calibration... 0.76% of reading (7,600 ppm) max Gain 1 with gain error adjusted to 0 at gain = 1 ... 0.5% of reading (500 ppm) max © National Instruments Corporation Board Gain Board Range (Software...
  • Page 83 45 pF Gain CMRR at 60 Hz 75 dB 105 dB Gain Accuracy 0.2% ( LSB) 14 s 20, 50 20 s 33 s Gain 5 V Range 0.3 LSB rms 0.6 LSB rms © National Instruments Corporation Appendix A...
  • Page 84 0 LSB. From the relationship between the mean of the noise and the measured rms magnitude of the noise, the character of the noise can be determined. National Instruments has determined that the character of the noise in the Lab-PC+ is fairly Gaussian, and so the noise specifications given are the amounts of pure Gaussian noise required to produce our readings.

  • Page 85: Analog Output

    (a straight line), excepting noise. If a D/A system has been calibrated perfectly, then the relative accuracy specification reflects its worst-case absolute error. Lab-PC+ User Manual © National Instruments Corporation Appendix A...
  • Page 86 Base clock accuracy ... 0.01% Max source frequency ... 8 MHz Min source pulse duration ... 60 ns Min gate pulse duration... 50 ns Data transfers ... Programmed I/O © National Instruments Corporation Level Input low voltage -0.3 V Input high voltage 2.2 V...
  • Page 87 Lab-PC+ User Manual Level Input low voltage -0.3 V Input high voltage 2.2 V Output low voltage = 4 mA) Output high voltage = -1 mA) 3.7 V © National Instruments Corporation Appendix A 0.8 V 5.3 V 0.45 V...

  • Page 88: Appendix Boki 82C53 Data Sheet

    This appendix contains the manufacturer data sheet for the OKI 82C53 System Timing Controller integrated circuit (OKI Semiconductor). This circuit is used on the Lab-PC+. Copyright © OKI Semiconductor 1991. Reprinted with permission of copyright owner. All rights reserved. OKI Semiconductor. Microprocessor Data Book 1990/1991. © National Instruments Corporation Lab-PC+ User Manual...

  • Page 100: Appendix Coki 82C55A Data Sheet

    Peripheral Interface integrated circuit (OKI Semiconductor). This circuit is used on the Lab-PC+. Copyright © OKI Semiconductor 1991. Reprinted with permission of copyright owner. All rights reserved. OKI Semiconductor. Microprocessor Data Book 1990/1991. © National Instruments Corporation Lab-PC+ User Manual...

  • Page 117: Register Map And Descriptions

    The register map for the Lab-PC+ is given in Table D-1. This table gives the register name, the register address offset from the board's base address, the type of the register (read-only, write- only, or read-and-write), and the size of the register in bits. © National Instruments Corporation Lab-PC+ User Manual...

  • Page 118: Table D-1. Lab-Pc+ Register Map

    Write-only 8-bit Write-only 8-bit Write-only 8-bit Read-and-write 8-bit Read-and-write 8-bit Read-and-write 8-bit Write-only 8-bit Write-only 8-bit Read-and-write 8-bit Read-and-write 8-bit Read-and-write 8-bit Write-only 8-bit Read-and-write 8-bit Read-and-write 8-bit Read-and-write 8-bit Write-only 8-bit Write-only 8-bit Write-only 8-bit © National Instruments Corporation...

  • Page 119: Register Description Format

    The bit map field for some write-only registers state not applicable, no bits used. Writing to these registers causes some event to occur on the Lab-PC+, such as clearing the analog input circuitry. The data is ignored when writing to these registers; therefore, any bit pattern will suffice. © National Instruments Corporation Lab-PC+ User Manual...

  • Page 120: Configuration And Status Register Group

    A/D conversion, A/D conversion error, and the status of the interrupts. When you start up your PC, all bits of the Command Registers are cleared. Bit descriptions for the registers in the Configuration and Status Register Group are given on the following pages. Lab-PC+ User Manual © National Instruments Corporation...
  • Page 121 SCANEN is then cleared (with MA<2..0> still set to 011), only analog input Channel 3 is sampled during the subsequent data conversions. GAIN<2..0> These three bits select the gain setting as follows: © National Instruments Corporation GAIN0 TWOSCMP GAIN<2..0> Selected Gain 1.25...
  • Page 122 Scanning in Appendix E, Register-Level Programming, for the correct sequence involved in setting the SCANEN bit. Lab-PC+ User Manual /D (bit 3 of Command Register 4). Input Selected Analog Input Channels MA<2..0> Single-Ended Appendix D DIFF Scan Disabled Scan Enabled © National Instruments Corporation...
  • Page 123 This bit indicates if an overflow error has occurred. If this bit is cleared, no error was encountered. If this bit is set, the A/D FIFO has overflowed because the data acquisition servicing operation could not keep up with the sampling rate. © National Instruments Corporation DMATC CNTINT OVERFLOW...
  • Page 124 FIFO. This bit is cleared if the FIFO is empty. After writing to the ADCLR Register this bit is set. Two 8-bit readings of FIFO are needed to clear this bit. Lab-PC+ User Manual © National Instruments Corporation Appendix D...
  • Page 125 The timebase for Counter B0 is fixed at 2 MHz and cannot be changed. The interval between acquired samples is the value loaded into Counter A0 multiplied by the period of the output signal from Counter B0. © National Instruments Corporation 2SDAC0 TBSEL SWTRIG...
  • Page 126 SWTRIG, but the Counter A1 (the sample counter) does not begin decrementing until a rising edge is detected on EXTTRIG. To use this mode, the HWTRIG bit should be cleared. Lab-PC+ User Manual D-10 © National Instruments Corporation Appendix D...
  • Page 127 DMA terminal count pulse is received. If TCINTEN is set, an interrupt request is generated when the DMA Controller Transfer Count Register decrements from 0 to FFFF (hex). The interrupt is serviced by writing to the DMATCINT Clear Register. © National Instruments Corporation ERRINTEN CNTINTEN TCINTEN D-11...
  • Page 128 DMAEN is set, a DMA request is generated whenever an A/D conversion result is available to be read from the FIFO. If DMAEN is cleared, no DMA request is generated. Lab-PC+ User Manual D-12 © National Instruments Corporation Appendix D...
  • Page 129 (2,3), (4,5) or (6,7) depending on the channel selection bits. This bit defaults to zero on reset, thus choosing the single-ended mode. Refer to the following table for choosing the appropriate mode. © National Instruments Corporation ECLKRCV ECLKDRV W4 Configuration...
  • Page 130 I/O Connector. If interval scanning is enabled (INTSCAN = 1), the clock source for Counter A0 also drives CLKB1. The source can be further selected by using the TBSEL bit in command register 2. This bit is cleared on reset. Lab-PC+ User Manual D-14 © National Instruments Corporation Appendix D...

  • Page 131: Analog Input Register Group

    Clear Register clears the data acquisition circuitry. Writing to the DMATC Clear Register clears the interrupt request generated by a DMA terminal count pulse. Bit descriptions for the registers making up the Analog Input Register Group are given on the following pages. © National Instruments Corporation D-15 Lab-PC+ User Manual...
  • Page 132 Values made up of D<11..0>, therefore, range from 0 to +4,095 decimal (0000 to 0FFF hex). Straight binary mode is useful for unipolar analog input readings because all values read reflect a positive polarity input signal. Lab-PC+ User Manual D-16 © National Instruments Corporation Appendix D...
  • Page 133 These bits contain the low byte of the 16-bit, sign-extended two's complement result of a 12-bit A/D conversion. The first of two consecutive readings of A/D FIFO Register always returns this byte. © National Instruments Corporation D-17 Register Map and Descriptions Lab-PC+ User Manual...
  • Page 134 FIFO. The data that is read should be ignored. Address: Base address + 08 (hex) Type: Write-only Word Size: 8-bit Bit Map: Not applicable, no bits used Lab-PC+ User Manual D-18 © National Instruments Corporation Appendix D...
  • Page 135 EXTCONV* signal. If the Start Convert Register is to initiate an A/D conversion, the Counter A0 output should be initialized to high state, which must be followed by an ADCLEAR operation, by writing to the ADCLEAR Register. © National Instruments Corporation Register Map and Descriptions D-19...
  • Page 136 Writing to the DMA Terminal Count (DMATC) Clear Register clears the interrupt request asserted when a DMA terminal count pulse is detected. Address: Base address + 0A (hex) Type: Write-only Word Size: 8-bit Bit Map: Not applicable, no bits used Lab-PC+ User Manual D-20 © National Instruments Corporation Appendix D...

  • Page 137: Analog Output Register Group

    12-bit DACs in the two analog output channels. DAC0 controls analog output Channel 0. DAC1 controls analog output Channel 1. These DACs should be written to individually. Bit descriptions of the registers making up the Analog Output Register Group are given on the following pages. © National Instruments Corporation D-21 Lab-PC+ User Manual...
  • Page 138 These eight bits are loaded into the specified DAC low byte. The low byte should be loaded first, followed by corresponding high byte loading. Lab-PC+ User Manual Load DAC0 low byte. Load DAC0 high byte. Load DAC1 low byte. Load DAC1 high byte. D-22 © National Instruments Corporation Appendix D...
  • Page 139 Interrupt Clear Register clears the interrupt request asserted when a low pulse is detected on the output of Counter A2 or on the EXTUPDATE* line. Bit descriptions for the registers in the Counter/Timer Register Groups are given in the following pages. © National Instruments Corporation D-23 Lab-PC+ User Manual...
  • Page 140 The Counter A0 Data Register is used for loading and reading back contents of 8253(A) Counter 0. Address: Base address + 14 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: Name Description D<7..0> 8-bit Counter A0 contents. Lab-PC+ User Manual D-24 © National Instruments Corporation Appendix D...
  • Page 141 The Counter A1 Data Register is used for loading and reading back contents of 8253(A) Counter 1. Address: Base address + 15 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: Name Description D<7..0> 8-bit Counter A1 contents. © National Instruments Corporation D-25 Register Map and Descriptions Lab-PC+ User Manual...
  • Page 142 The Counter A2 Data Register is used for loading and reading back contents of 8253(A)Counter A2. Address: Base address + 16 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: Name Description D<7..0> 8-bit Counter A2 contents. Lab-PC+ User Manual D-26 © National Instruments Corporation Appendix D...
  • Page 143 The Counter A Mode Register is an 8-bit register. Bit descriptions for each of these bits are given in Appendix B, OKI 82C53 Data Sheet. Address: Base address + 17 (hex) Type: Write-only Word Size: 8-bit Bit Map: © National Instruments Corporation D-27 Register Map and Descriptions Lab-PC+ User Manual...
  • Page 144 Counter A2 output or on EXTUPDATE* line. Address: Base address + 0C (hex) Type: Write-only Word Size: 8-bit Bit Map: Not applicable, no bits used. Lab-PC+ User Manual D-28 © National Instruments Corporation Appendix D...
  • Page 145 The Counter B0 Data Register is used for loading and reading back the contents of 8253(B) Counter 0. Address: Base address + 18 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: Name Description D<7..0> 8-bit Counter B0 contents. © National Instruments Corporation D-29 Register Map and Descriptions Lab-PC+ User Manual...
  • Page 146 The Counter B1 Data Register is used for loading and reading back the contents of 8253(B) Counter 1. Address: Base address + 19 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: Name Description D<7..0> 8-bit Counter B1 contents. Lab-PC+ User Manual D-30 © National Instruments Corporation Appendix D...
  • Page 147 The Counter B2 Data Register is used for loading and reading back the contents of 8253(B) Counter 2. Address: Base address + 1A (hex) Type: Read-and-write Word Size: 8-bit Bit Map: Name Description D<7..0> 8-bit Counter B2 contents. © National Instruments Corporation D-31 Register Map and Descriptions Lab-PC+ User Manual...
  • Page 148 The Counter Mode Register is an 8-bit register. Bit descriptions for each of these bits are given in Appendix B, OKI 82C53 Data Sheet, of this manual. Address: Base address + 1B (hex) Type: Write-only Word Size: 8-bit Bit Map: Lab-PC+ User Manual D-32 © National Instruments Corporation Appendix D...
  • Page 149 I/O ports (A, B, and C) of the 8255A. These ports can be programmed as two groups of 12 signals or as three individual 8-bit ports. Bit descriptions for the registers in the Digital I/O Register Group are given on the following pages. © National Instruments Corporation D-33 Lab-PC+ User Manual...
  • Page 150 I/O Circuitry in Appendix E, Register-Level Programming, for information on how to configure Port A for input or output. Address: Base address + 10 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: Name Description D<7..0> 8-bit Port A data. Lab-PC+ User Manual D-34 © National Instruments Corporation Appendix D...
  • Page 151 I/O Circuitry in Appendix E, Register-Level Programming, for information on how to configure Port B for input or output. Address: Base address + 11 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: Name Description D<7..0> 8-bit Port B data. © National Instruments Corporation D-35 Register Map and Descriptions Lab-PC+ User Manual...
  • Page 152 Port C Register. Address: Base address + 12 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: Name Description D<7..0> 8-bit Port C data. Lab-PC+ User Manual D-36 © National Instruments Corporation Appendix D...
  • Page 153 Programming, for a description of the individual bits in the Digital Control Register. Address: Base address + 13 (hex) Type: Write-only Word Size: 8-bit Bit Map: Name Description CW<7..0> 8-bit control word. © National Instruments Corporation D-37 Register Map and Descriptions Lab-PC+ User Manual...
  • Page 154 Interval Counter decrements with each conversion. When the count reaches 0, the Interval Counter autoinitializes, restoring the original count value. Bit descriptions for the registers in the Interval Counter Register Group are given on the following pages. Lab-PC+ User Manual D-38 © National Instruments Corporation...
  • Page 155 Single-Channel Interval Acquisition Mode in Appendix E, Register-Level Programming, for a description of the programming sequence. Address: Base address + 1E (hex) Type: Write-only Word Size: 8-bit Bit Map: Name Description D<7..0> Interval Counter count. © National Instruments Corporation D-39 Register Map and Descriptions Lab-PC+ User Manual...
  • Page 156 Word Size: 8-bit Bit Map: Name Description Each of these bits must be 0 for proper operation of the Lab-PC+. This bit must be 1 for proper operation of the Lab-PC+. Lab-PC+ User Manual D-40 © National Instruments Corporation Appendix D...

  • Page 157: Register-Level Programming

    4. Write 00 (hex) to the Command Register 4. 5. Write 34 (hex) to Counter A Mode Register. 6. Write 0A (hex) to Counter A0 Data Register. 7. Write 00 (hex) to Counter A0 Data Register. © National Instruments Corporation Lab-PC+ User Manual...

  • Page 158: Programming The Analog Input Circuitry

    A/D conversion result, and how to clear the analog input circuitry. Ensure that you have selected the appropriate analog input mode through jumper W4 and bit 3 of Command Register 4. Lab-PC+ User Manual © National Instruments Corporation Appendix E...
  • Page 159 Reading the A/D FIFO Register removes the A/D conversion result from the A/D FIFO. The binary modes of the A/D FIFO output are explained in the next section, A/D FIFO Output Binary Modes. © National Instruments Corporation Register-Level Programming Lab-PC+ User Manual...

  • Page 160: Table E-1. Unipolar Input Mode A/D Conversion Values (Straight Binary Coding

    Range: 0 to +10 V (Decimal) (Hex) 0000 1,024 0400 2,048 0800 3,072 0C00 4,095 0FFF A/D Conversion Result Range: -5 to +5 V Decimal -2,048 F800 -1,024 FC00 0000 1,024 0400 2,047 07FF © National Instruments Corporation Appendix E...

  • Page 161: Clearing The Analog Input Circuitry

    Counter A0 after the required number of conversions have been obtained. The number of conversions in a single data acquisition operation in this case is unlimited. Counter A0 is clocked by a 1 MHz clock on start up. © National Instruments Corporation Register-Level Programming Lab-PC+ User Manual...
  • Page 162 Write the most significant byte of the timebase count to the Counter B Data Register. For example, programming a timebase of 10 s requires a timebase count of 10 s 0.5 s =20 Lab-PC+ User Manual © National Instruments Corporation Appendix E...
  • Page 163 8-bit reads from the A/D FIFO. Ignore the data obtained in the read. 5. Start and service the data acquisition operation. To start the data acquisition operation, set the SWTRIG bit in Command Register 2. This enables Counter A0 to start counting. © National Instruments Corporation Register-Level Programming Lab-PC+ User Manual...
  • Page 164 A/D conversions that have occurred (that is, the sample count) is maintained by software in this case. With this arrangement, data acquisition operations can acquire more than 65,535 samples. The following programming steps are required for a data acquisition operation in freerun acquisition mode: Lab-PC+ User Manual © National Instruments Corporation Appendix E...
  • Page 165 Write the least significant byte of the sample interval to the Counter A0 Data Register. c. Write the most significant byte of the sample interval to the Counter A0 Data Register. © National Instruments Corporation Register-Level Programming Lab-PC+ User Manual...
  • Page 166 OVERRUN bit in the Status Register is set. The minimum recommended sampling interval on the Lab-PC+ is 16 s. Both the OVERFLOW and OVERRUN bits in the Status Register are cleared by writing to the A/D Clear Register. Lab-PC+ User Manual E-10 © National Instruments Corporation Appendix E...
  • Page 167 Pretriggering is set up by setting PRETRIG in Command Register 2. PRETRIG supersedes HWTRIG; if both bits are set, then pretriggering is enabled. © National Instruments Corporation E-11 Lab-PC+ User Manual...
  • Page 168 Command Register 1 earlier in this chapter for gain and analog input channel bit descriptions. To use posttrigger mode, the PRETRIG bit and SWTRIG bit in Command Register 2 must be cleared. Lab-PC+ User Manual E-12 © National Instruments Corporation Appendix E...
  • Page 169 DMA or interrupts can also be used to service the data acquisition operation. These topics are discussed in the A/D Interrupt Programming and Programming DMA Operation sections later in this appendix. © National Instruments Corporation Register-Level Programming E-13 Lab-PC+ User Manual...
  • Page 170 Command Register 1 earlier in this chapter for gain and analog input channel bit descriptions. To select pretrigger mode, set the PRETRIG bit and clear the HWTRIG bit in Command Register 2. Lab-PC+ User Manual E-14 © National Instruments Corporation Appendix E...
  • Page 171 Write the most significant byte of (M), where M is the sample count, after the trigger to the Counter A1 Data Register. After you complete this programming sequence, counter A1 is configured to count A/D conversion pulses and EXTTRIG input is enabled. © National Instruments Corporation Register-Level Programming E-15 Lab-PC+ User Manual...
  • Page 172 GATA0 is set low. GATA0 can be set low by writing 34 (hex) to the Counter A Mode Register after the required number of samples is obtained. This disables EXTCONV*, that is, further transitions on EXTCONV* are ignored. Lab-PC+ User Manual E-16 © National Instruments Corporation Appendix E...
  • Page 173 OUTB1 line. The period of this signal must be at least as long as the channel-scanning cycle. While using the interval-scanning mode, the SCANEN bit in the Analog Configuration Register is used to gate the operation of the INTSCAN bit until the data © National Instruments Corporation Register-Level Programming E-17...
  • Page 174 (N * sample interval). A software trigger starts the sampling sequence. The Lab-PC+ takes N samples on the specified channel, after which acquisition halts until the next interval pulse is generated on OUTB1. The Lab-PC+ takes Lab-PC+ User Manual E-18 © National Instruments Corporation Appendix E...
  • Page 175 To use the conversion interrupt, set the FIFOINTEN bit in Command Register 3. If this bit is set, an interrupt is generated whenever the DAVAIL bit in the Status Register is set. This interrupt condition is cleared when the FIFO is emptied by reading its contents. © National Instruments Corporation Register-Level Programming E-19...

  • Page 176: Programming The Analog Output Circuitry

    Counter A (OUTA2). The LDAC bits in Command Register 2 determine which update method is used. If LDAC0 is set high, the analog output from DAC0 is Lab-PC+ User Manual E-20 © National Instruments Corporation Appendix E...

  • Page 177: Table E-3. Analog Output Voltage Versus Digital Code

    2SDAC bit in Command Register 2. Table E-3. Analog Output Voltage Versus Digital Code (Unipolar Mode, Straight Binary Coding) Digital Code (Decimal) 2,048 4,095 © National Instruments Corporation Voltage Output (Hex) 0000 0001 2.4414 mV 0800 5.0 V...

  • Page 178: (Bipolar Mode, Two's Complement Coding

    Counter A2 must be programmed in Mode 2 with the appropriate update interval. Lab-PC+ User Manual Voltage Output (Hex) = 10 V) F800 -5.0 V FC00 2.5 V 0000 0.0 V 0400 2.5 V 07FF 4.9976 V E-22 © National Instruments Corporation Appendix E...
  • Page 179 (that is, Mode 0, Mode 1, or Mode 2). When the control-word flag is 0, bits 3 through 0 specify the bit set/reset format of Port C. © National Instruments Corporation Register-Level Programming...

  • Page 180: Figure E-1. Control-Word Format With Control-Word Flag Set

    1 = input 0 = output Port B 1 = input 0 = output Mode Selection 0 = Mode 0 1 = Mode 1 Bit Set/Reset 1 = set 0 = reset Bit Select (000) (001) (010) (111) © National Instruments Corporation...
  • Page 181 The 16 possible I/O configurations are shown in Table E-5. Notice that bit 7 of the control word is set when programming the mode of operation for each port. © National Instruments Corporation Register-Level Programming E-25...

  • Page 182: Table E-5. Mode 0 I/O Configurations

    Output Output Output Output Output Input Output Input Input Output Input Output Input Input Input Input E-26 © National Instruments Corporation Appendix E Group B Port C Output Input Output Input Output Input Output Input Output Input Output Input Output...
  • Page 183 During a Mode 1 data read transfer, the status of the handshaking lines and interrupt signals can be obtained by reading Port C. The Port C status-word bit definitions for an input transfer are shown next. © National Instruments Corporation Port C bits PC6 and PC7 1 = input...
  • Page 184 Notice that the status of STBA* and STBB* is not provided in the Port C status word. Lab-PC+ User Manual INTEA INTRA Group A IBFA STBA* INTRA STBB* Group B IBFB INTRB E-28 Appendix E INTEB IBFB INTRB © National Instruments Corporation...
  • Page 185 During a Mode 1 data write transfer, the status of the handshaking lines and interrupt signals can be obtained by reading Port C. Notice that the bit definitions are different for a write and a read transfer. © National Instruments Corporation Port C bits PC4 and PC5 1 = input...
  • Page 186 Notice that the status of ACKA* and ACKB* is not provided when Port C is read. Lab-PC+ User Manual INTRA OBFA* ACKA* Group A INTRA ACKB* Group B OBFB* INTRB E-30 Appendix E INTEB OBFB* INTRB © National Instruments Corporation...
  • Page 187 Mode 0 or Mode 1. If Port B is configured for Mode 0, then PC2, PC1, and PC0 of Port C can be used as extra input or output lines. © National Instruments Corporation Register-Level Programming...
  • Page 188 Lab-PC+ User Manual Port C bits (PC2-PC0) 1 = input 0 = output Port B direction 1 = input 0 = output Group B Mode 0 = Mode 0 1 = Mode 1 INTE2 INTRA E-32 Appendix E © National Instruments Corporation...

  • Page 189: Table E-6. Port C Set/Reset Control Words

    Port C. Table E-6. Port C Set/Reset Control Words Bit Set Control Word 0xxx0001 0xxx0011 0xxx0101 0xxx0111 0xxx1001 0xxx1011 0xxx1101 0xxx1111 © National Instruments Corporation OBFA* ACKA* IBFA STBA* Group A INTRA Bit Reset Control Word 0xxx0000 0xxx0010 0xxx0100...
  • Page 190 PC0 or PC3 for input and connect the external signal that should trigger an interrupt to PC0 or PC3. When the external signal becomes logic high, an interrupt request occurs. To negate the interrupt request, the external signal must become logic low. Lab-PC+ User Manual E-34 © National Instruments Corporation...

  • Page 191: Appendix F Customer Communication

    Filling out a copy of the Technical Support Form before contacting National Instruments helps us help you better and faster. National Instruments provides comprehensive technical assistance around the world. In the U.S. and Canada, applications engineers are available Monday through Friday from 8:00 a.m. to 6:00 p.m.

  • Page 192: Technical Support Form

    National Instruments for technical support helps our applications engineers answer your questions more efficiently. If you are using any National Instruments hardware or software products related to this problem, include the configuration forms from their user manuals. Include additional pages if necessary.

  • Page 193: Other Products

    Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.

  • Page 194: Documentation Comment Form

    Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: Lab-PC+ User Manual Edition Date: June 1996 Part Number: 320502B-01 Please comment on the completeness, clarity, and organization of the manual.
  • Page 195 EISA Extended Industry Standard Architecture farads FIFO first-in-first-out feet hexadecimal hertz input/output inches ksamples 1,000 samples light-emitting diode least significant bit megabytes of memory meters most significant bit © National Instruments Corporation Value Glossary-1 Lab-PC+ User Manual...
  • Page 196 System Development Kit system timing controller transistor-to-transistor logic volts volts direct current external volts volts, input high volts, input low V in volts in volts, output high volts, output low output voltage reference voltage Lab-PC+ User Manual Glossary-2 © National Instruments Corporation...
  • Page 197 A/D conversions using interval scanning, E-18 single-channel interval acquisition mode, E-19 Counter B2 Data Register, D-31 overview, D-23 © National Instruments Corporation register map, D-2 Timer Interrupt Clear Register, D-28 8255A Digital I/O Register Group, D-33 to D-37 Digital Control Register, D-37...
  • Page 198 E-4 DMATC Interrupt Clear Register, D-20 overview, D-15 register map (table), D-2 Start Convert Register, D-19 analog input signal connections, 3-4 to 3-5 exceeding input ranges (warning), 3-4 input ranges and maximum ratings, 3-4 Index-2 © National Instruments Corporation...
  • Page 199 A-4 transfer characteristics, A-4 voltage output, A-4 base I/O address selection, 2-3 to 2-5 © National Instruments Corporation example switch settings (figure), 2-4 factory settings (table), 2-3 possible settings with corresponding base I/O address and base address I/O space...
  • Page 200 2-9 to 2-10 bipolar output selection, 2-9 jumper settings (table), 2-9 unipolar output selection, 2-10 board base I/O address selection, 2-3 to 2-5 DMA channel selection, 2-6 to 2-7 interrupt selection, 2-7 to 2-8 Index-4 © National Instruments Corporation...
  • Page 201 E-12 to E-16 posttrigger mode, E-12 to E-14 pretrigger mode, E-14 to E-16 overview, E-5 programming steps, E-6 to E-8 © National Instruments Corporation single input channel, E-6 to E-8 CONVERT signal, posttrigger data acquisition timing (figure), 3-22 Counter A Mode Register...
  • Page 202 Mode 0 operation, E-25 to E-26 control words, E-25 to E-26 programming examples, E-26 Mode 1 input, E-27 to E-28 control words, E-27 Port C pin assignments, E-28 Port C status-word bit definitions, E-28 programming example, E-29 Index-6 © National Instruments Corporation...
  • Page 203 DMA request generation, E-20 DMATC Interrupt Clear Register description, D-20 DMA request generation, E-20 documentation conventions used in manual, xii National Instruments documentation, xiii organization of manual, xi-xii © National Instruments Corporation ECKDRV bit, D-14 ECLKRCV bit, D-13 environment specifications, A-6...
  • Page 204 Port C signal assignments (table), 3-16 IBFA status word, Port C Mode 1 input, E-28 Mode 2 operation, E-32 IBFB status word, Port C, E-28 initializing Lab-PC+, E-1 to E-2 input configurations, 3-7 to 3-27 Index-8 © National Instruments Corporation...
  • Page 205 EXTUPDATE* signal (figure), 3-24 types of interrupts, 4-3 to 4-4 Interval Counter Register Group, D-38 to D-40 Interval Counter Data Register © National Instruments Corporation description, D-39 single-channel interval acquisition mode, E-19 Interval Counter Strobe Register, D-40 overview, D-38...
  • Page 206 E-5 to E-10 controlled acquisition mode, E-6 to E-8 freerun acquisition mode, E-8 to E-10 single-channel interval acquisition mode, E-18 to E-19 multiple-channel (scanned) data acquisition, 4-6 to 4-7 multiplexers, analog input, 4-5 Index-10 © National Instruments Corporation...
  • Page 207 OVERRUN bit A/D FIFO overrun condition clearing the analog input circuitry, E-5 controlled acquisition programming, E-8 posttrigger mode, E-14 © National Instruments Corporation pretrigger mode, E-16 freerun acquisition programming, E-10 A/D interrupt programming, E-20 description, D-8 PAO<0..7> signal (table), 3-3 PBO<0..7>...
  • Page 208 3-25 RD* signal description, 3-17 Mode 1 input timing, 3-18 Mode 2 bidirectional timing, 3-20 referenced single-ended input. See RSE input (eight channels). registers, D-1 to D-40. See also specific register groups and individual registers. Index-12 © National Instruments Corporation...
  • Page 209 3-4 to 3-5 analog output connections, 3-12 to 3-13 cabling considerations, 3-28 digital I/O connections, 3-13 to 3-20 © National Instruments Corporation illustration, 3-15 Mode 1 input timing, 3-18 Mode 1 output timing, 3-19 Mode 2 bidirectional timing, 3-20...
  • Page 210 3-21 to 3-28 data acquisition timing connections, 3-21 to 3-24 EXTCONV* signal timing (figure), 3-21 EXTUPDATE* signal timing generating interrupts (figure), 3-24 updating DAC output (figure), 3-24 posttrigger timing (figure), 3-22 pretrigger timing (figure), 3-23 Index-14 © National Instruments Corporation...
  • Page 211 A-6 two-channel interval-scanning timing (figure), 4-13 TWOSCMP bit description, D-6 returning A/D conversion result, E-4 © National Instruments Corporation unipolar input mode configuration, 2-14 unipolar input signal range versus gain (table), 4-8 voltage versus A/D conversion values (table), E-4...

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