Tandy 1400LT Service Manual page 46

Figure 4-12 RAM-3 shows the DRAM and peripheral circuitry.
ADL- lOOSP 10 signal is generated by the IC45 (Active time delay line) and it affects Column-address-strobe timing.
(CASO, CAS1, and
a)
--
A 0
A 1
A 2
A 3
A 1 4
A
15
A 1 6
P
I j .
A 1 2
74HC 157
4 8
1 A 3 Y
2 A
- # =
I C 4 0
*
7 4 H C 1 5 7
G 7 , A - L
I
28
38 2 Y
48
1 A 3 Y
2A
3 A 4 Y
I 1 2
1
I C 4 3 IC300 I C 3 0 2
A 0 A 0
1
04- i
P
C A S 0
C A S 1
C A S 2
MREQ
-
m
MW
1
A 7
-
A 7
-
A 6 A 7 .
-
D R A H P i
5
00
DO DO
03 03
I - I t
4
s
03
I
IC44
IC30
1 IC303
I C 3 0 6
(305. 306)
T I M I N G . A O D R E S S
C O N T R O L
I
BUS
C O N T R O L L E R
-
30nemc
1
. -
. *
. .
-
. .
MREQ
-
. .
*
MREQ
A D L - 1 0 0 S P 4
A O L - 1 O O S P l O
A O L - l O O S P 4
A O L - 1 O O S P l O
. .
. .
. -
60naec
. .
Figure 4-12. RAM-3
4-9