Tandy 1400LT Service Manual page 283

3DAH (STATUS REGISTER)
The status register is a 5 bit read-only register. Its address is hex "3DA" of the four least significant bit of I/O
address with "0" *IOSEL signal.
The following is a description of the register functions.
BIT NAME FUNCTION
0 DISP. EN.
1 LPD/MS 1
2 LPS/MSO
3 VSYNC
4 VIDEO
5
6
7
~ ~
DISPLAY ENABLE TIMING
LIGHT PEN TRIGGER SET or MOUSE SWITCH I
LIGHT PEN SWITCH or MOUSE SWITCH 0
VERTICAL RETRACE TIMING
VIDEO DOT
NOT USED
NOT USED
NOT USED
STATUS REGISTER
Bit 0
Bit 1
When set, this bit indicates the display disabled timing signal on retracing.
When the Light Pen is selected, this bit "1" indicates that a positive-going edge from the light pen input
has set the Light Pen Trigger flip-flop. This bit can be cleared by executing I/O OUT command to
address hex "B" with any data.
When the Mouse is selected, this bit indicates the status of the Mouse Switch 1. The switch is not
debounced and is not latched. When this bit is "0", the Mouse Switch 1 is "on".
This bit indicates the status of the Light Pen Switch or Mouse Switch 0. These switches are not
debounced and are not latched. When this bit is "O", the switch which is selected by the expanded mode
register, is "on".
When "l", this bit indicates the vertical retrace signal is "active", and if the Monochrome Adapter Mode
is selected, this bit becomes the video-dot information as the same as bit 4.
Bit 2
Bit 3
3DDH, 3DEH (REGISTER BANK Address/Data)
All of the new expanded functions are implemented in the Register Bank.
This Register Bank includes the Sprite Pattern and its location data, Color Palette Register #O
to #15 data,
display monitor configuration control data and memory configuration control data.
Registers within this bank are programmed by first writing a register address pointer to port hex "3DD" and then
writing the data to port hex "3DE'. The register address is incremented by one after a port hex "3DE' write
operation.
The bit 7 of port hex "3DD" has a special function and is named the Protect Bit. When this bit sets, the bit 6 and
bit 7 on the Mode Select Register can be active.
The following registers are defined on the Register Bank in the LCDC.
F-14