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Sony RDR-GXD500 Service Manual page 18

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RDR-GXD500
Q Q
3 7 6 3 1 5 1 5 0
1
2
3
A-003 BOARD(1/3)
NO MARK:REC/PB MODE
EMMA2L
:Voltage measurement of the CSP IC
A
and the Transistors with
-REF.NO.:50000 SERIES-
not possible.
GP_JIG_MODE
TXD1B
TXD1B
RXD1B
1
TO(3/3)
RXD1B
B
PMSBS
PMSBS
PMSDIO
PMSDIO
PMSINS
PMSINS
PMSPON
PMSPON
PMSSCLK
PMSSCLK
C
B+
+3V3
C103
C106
C111
C100
0.1u
10u
4.7u
0.1u
16V
F
B
16V
B+
10V
16V
+2V5
2
TO(3/3)
D
C101
C104
C107
0.1u
10u
4.7u
16V
F
B
B+
16V
10V
+1V5
GND
C102
C105
C108
C113
0.1u
0.1u
10u
4.7u
B
16V
F
16V
16V
10V
E
R400
10k
FCS1B
FCS1B
FWEB
FWEB
FOEB
FOEB
3
TO(2/3)
NAND_ALE
SPDIF
F
NAND_CLE
NAND_R/BB
4
EMMA_RESET
G
TO(2/3,3/3)
VID_CR
RB103
47X4
AMCK
ABCK
5
ADO
TO(3/3)
ALRCK
T E
L
1 3 9 4 2 2 9 6 5 1 3
VID_Y
VID_CB
H
I
J
SDA0
SCL0
GPIO_2
K
6
TO(3/3)
GPIO_1
GPIO_3
RB106
47X4
GPIO_4
GP_FE_RESET
7
TO(3/3)
SDA1
SCL1
L
RDATA[0]
RDATA[0]
RDATA[1]
RDATA[1]
RDATA[2]
RDATA[2]
M
RDATA[3]
RDATA[3]
RDATA[4]
RDATA[4]
RDATA[5]
RDATA[5]
RDATA[6]
RDATA[6]
RDATA[7]
8
TO(2/3)
RDATA[7]
RDATA[8]
RDATA[8]
RDATA[9]
RDATA[9]
9
TO(2/3)
RDATA[10]
RDATA[10]
N
RDATA[11]
RDATA[11]
RDATA[12]
RDATA[12]
RDATA[13]
RDATA[13]
RDATA[14]
RDATA[14]
RDATA[15]
RDATA[15]
w w w
O
P
EMMA2L
A-003 (1/3)
4
5
6
7
8
mark,is
B+
C122
0.1u
B
B+
16V
B+
C115
C123
C118
C119
0.1u
0.1u
0.1u
0.1u
B
B
B
B
B
16V
16V
16V
16V
204
203
202
201
200
C112
C116
C120
C124
0.1u
0.1u
0.1u
0.1u
B
B
B
B
16V
16V
16V
16V
C134
C136
0.1u
0.1u
VDD1
B
B
C127
16V
16V
GND
0.1u
B
C135
C117
C121
C125
C126
16V
GND
0.1u
0.1u
0.1u
0.1u
0.1u
B
B
B
B
B
B
CBPC
C128
16V
16V
16V
16V
16V
0.1u
B
CBPD
16V
RB404
CBPE
10kX4
C129
JTCL
AGND4
0.1u
PMSINS
B
16V
DSR1B/PMSINS
RDATA[11]
RDATA11/HSD3
RDATA[5]
RDATA5
RDATA[12]
RDATA12/HSD4
NAND_ALE
ATX
ADO
PPORT2
PMSSCLK
PPORT5/PMSSCLK
PMSPON
DCD1B/PMSPON
TEST
R108
100
SDA0
JTDI
JTRST
R102
100
RSTSWB
VAR
AVDD1
JL409
C132
AGND2
470p
CH
AVDD3
50V
AVDD4
AVDD5
OFF0
RDATA[4]
RDATA4
NAND_CLE
JL126
TXD1B
ALRCK
ABCK
PPORT1
PPORT4
PMSBS
RI1B/PMSBS
TMODE2
EDINT
R113
100
SCL0
R149
JTDO
CL130
JL130
10k
NMI
JL101
CL101
EIVHS
AGND1
R151
10k
CBPB
C130
0.1u
AVDD0
B
16V
VACOMP
AVDD2
RDATA[3]
RDATA3
NAND_R/BB
JL100
CL100
R105
47
GCSB1
RXD1B
PWMOUT
AMCK
PPORT0
PPORT3
TMODE0
R193
4700
TMODE1
R196
100
R197
SDA1
100
SCL1
JTMS
R194
4700
RSTOUT
JL104
R150
10k
EIVVS
C131
CL104
0.1u
CBPA
B
16V
B+
AGND0
VAG
AGND3
VAB
DADD[0]
DADD[0]
DADD[1]
RB100
DADD[1]
10kX4
DADD[2]
DADD[2]
R192
DADD[3]
10k
DADD[3]
1
2
3
4
5
DADD[4]
DADD[4]
DADD[5]
DADD[5]
DADD[6]
DADD[6]
DADD[7]
DADD[7]
DADD[8]
DADD[8]
DADD[9]
DADD[9]
DADD[10]
DADD[10]
DADD[11]
DADD[11]
DADD[12]
DADD[12]
x
a o
.
i
RB113
10kX4
B+
4-7
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9
10
11
12
C133
0.1u
R130
B
16V
47
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
Q
Q
3
7
IC100
EMMA2L
IC100
UPD61120AF1-100-JN1-A
CSP(CHIP SIZE PACKAGE)IC
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
u 1 6 3
y
RB102
47X4
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2
4
8
9
9
13
14
15
16
17
B+
B+
B+
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
AGND1_16
AVDD1_16
AVSYSCLKIN
GND
GND
GND
GND
GND
VDD1
FE_DATA[4]
RADD22/STPDAT4
FE_VALID
RADD16/STPEN
FE_DATA[3]
RADD21/STPDAT3
EVCK
SYSCLKIN
AVDD1_162
VDD1
VDD1
VDD1
VDD1
VDD2
VDD1
RADD12
FE_DATA[5]
RADD23/STPDAT5
RADD15/STPCLK
AGND1_162
CLK27IN
AVDD1_266
6
3
1
5
1
5
0
8
9
R107
VDD3
47
FCSB0
FE_DATA[7]
RADD25/STPDAT7
RADD7
FE_DATA[6]
RADD24/STPDAT6
MCLKIN
AGND1_266
AGND1_6
GND
VDD3
RADD5
PPORT28
RADD6
VRCLKIN
AVDD1_6
CL140
VVS
VDD1
GND
GRDYB
RADD4
PPORT31
PPORT35
R115
47
FCSB1
CL141
VHS
PPORT43
JL120
PPORT33
RADD2
JL121
PPORT32
RADD3
VCK
STPERRB
R148
10k
PPORT42
CL142
VFIELD
DQ[1]
DQ1
DQ[3]
DQ3
DQ[5]
DQ5
DQ[7]
DQ7
DWEB
DWEB
GND2
VDD2
GND2
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
B+
B+
m
c o
.
4-8
2
8
9
9
18
19
20
21
FE_CLK
FE_CLK
FE_DATA[0]
FE_DATA[0]
FE_DATA[1]
FE_DATA[1]
FE_DATA[2]
FE_DATA[2]
FE_DATA[3]
FE_DATA[3]
FE_DATA[4]
FE_DATA[4]
FE_DATA[5]
FE_DATA[5]
FE_DATA[6]
FE_DATA[6]
FE_DATA[7]
FE_DATA[7]
FE_PACKET_SYNC
FE_PACKET_SYNC
FE_VALID
FE_VALID
10
TO(3/3)
VDO_D[1]
RB110
DTT_656_D[1]
DTT_656_D[1]
68x4
VDO_D[4]
DTT_656_D[4]
DTT_656_D[4]
VDO_D[0]
DTT_656_D[0]
DTT_656_D[0]
VDO_D[6]
DTT_656_D[6]
RB111
DTT_656_D[6]
68x4
VDO_D[2]
DTT_656_D[2]
DTT_656_D[2]
VDO_D[5]
DTT_656_D[5]
DTT_656_D[5]
VDO_D[3]
DTT_656_D[3]
DTT_656_D[3]
R152
68
VDO_CLK
DTT_656_CLK
DTT_656_CLK
VDO_EN
R153
68
DTT_656_EN
DTT_656_EN
VDO_D[7]
R154
68
DTT_656_D[7]
DTT_656_D[7]
FE_CLK
RB105
10kx4
2
4
9
8
2
9
9
CL117
JL117
CL112
JL112
RADD[5]
RADD[6]
RADD[4]
FCS1B
IC201
JL114
27MHz CLOCK GEN.
X200
C202
1p
27MHz
CK
50V
IC201
C203
KA5SDKASO1TSL
1p
VDO_CLK
CK
1.7
1.7
50V
X1
X2
3.3
VCC
GND
R238
C206
10k
3.3
0.1u
AIN
VCC
B
16V
1.7
1.7
GND
27M
C205
R237
C208
0.1u
1
0.1u
47
B
B
B+
16V
16V
C207
0.001u
B
50V
DQ[0]
DQ[0]
DQ[1]
DQ[1]
DBA0
DQ[2]
DBA0
DQ[2]
DBA1
DBA1
DQ[3]
DQ[3]
DCASB
DQ[4]
DCASB
DQ[4]
DCLK
DQ[5]
DCLK
DQ[5]
DCLKB
DQ[6]
DCLKB
DQ[6]
DCSB
DCSB
DQ[7]
11
DQ[7]
TO(2/3)
DQM0
12
TO(2/3)
DQ[8]
DQM0
DQ[8]
DQM1
DQ[9]
DQM1
DQ[9]
DQS0
DQS0
DQ[10]
DQ[10]
DQS1
DQS1
DQ[11]
DQ[11]
DRASB
DQ[12]
DRASB
DQ[12]
DVREF
DQ[13]
DVREF
DQ[13]
DWEB
DWEB
DQ[14]
DQ[14]
DQ[15]
DQ[15]
SIGNAL PATH
VIDEO SIGNAL
AUDIO
CHROMA
Y
Y/CHROMA
SIGNAL
REC
PB

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