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RDR-GXD500
Q Q
3 7 6 3 1 5 1 5 0
T E
L
1 3 9 4 2 2 9 6 5 1 3
w w w
3-6. POWER BLOCK DIAGRAM (2/3)
CN1801
UNSW 6V
1
FL
UNSW 3.3V
4
FL
TO
POWER
BLOCK
5
SW 2.5V
FL
6
9
SW 3.3V
FL
10
11
SW 3.3V
FL
12
P_CCONT
14
CN1904
12
UNSW 6V
13
AV-091 BOARD
CN1903
A5V
8
IC1601
2CH DAC
RD-050 BOARD
x
a o
y
.
i
3-11
http://www.xiaoyu163.com
8
UNSW 5V
IC1804
SW 5V
SW 5V
IC103
4
5
REG
3
SH
IC1803
IC201
3
IC204
UNSW 1.5V
UNSW 1.5V
1
REG
6
128Mbit
FLASH MEMORY
IC1802
3
SW 1.8V
SW 1.8V
1
IC501
REG
6
IC703
2
GPS3(HOST GLUE)
5
1.5V REG
4
IC701
5
3.3V REG
4
1
IC702
VIDEO DECODER
Q
Q
3
7
6
3
SW 3.3V
IC1306
V REF
IC1301
5
4
REG
NAZCA
u 1 6 3
.
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2
4
9
9
8
IC108
IC104
IC111
IC112
IC106
IC109
BUFFER
EEP ROM
BUFFER
CLOCK
256Mbit SDRAM
SH 3.3V
IC301
IC306
IC401
IC402
IC305
IC310
SWITCH
256Mbit NAND
FLASH MEMORY
SWA BUFFER
UNSW BUFFER
IC902
IC803
IC901
IC1101
IC1102
IC903
AV GLUE
AV ENCODER
MR PROCESS
256Mbit SDRAM
SDRAM
IC1201
5
4
1.8V REG
IC1202
IC1203
IC1206
AV DECODER
64Mbit SDRAM
512 FS
1
5
1
5
0
8
9
2
4
IC1304
IC1402
IC1501
IC1502
IC1702
IC1305
BUFFER
AUDY
16Mbit SDRAM
PLL
SDRAM
m
c o
3-12
2
9
9
CN103
7
NOT USE
6
9
8
2
9
9
IC1703
IC1701
IC1704
27MHz BUFFER
512 FS
256 FS
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