JVC KD-SV3000 Service Manual page 31

Pin No.
23
SEL_PLL1
24 RSTOUT_B
2:4,27:30,76
33
SEL_PLL0
37
41,51
42
43
44
45:46 AOR+,AOR-
47:48 AOL-,AOL+
49
50
52
53
54
55
56:57,62:63
58
59,60
61
64
65
71
74
79
80 2XPCLK
82 HSYN_B
84 VSYN_B
86:89,92,94,96,98 YUV[7:0]
Symbol I/O
RWS O Dual-purpose pin RWS is the audio frame sync.
I Pins SEL_PLL[1.0] select the PLL clock frequency for the DCLK output.
SEL_PLL1
0
0
1
1
O Reset output(active-low).
NC No connect.Do not connect to these pins.
RSD O Dual-purpose pin. RSD is the receive audio data input.
I SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the
DCLK output.See the table for pin number 23.
RBCK O Dual-purpose pin.RBCK is the receive audio bit clock.
SER_IN I SER_IN is the serial input DSC mode.
0-Parallel DSC mode.
1-Serial DSC mode.
VSSAA I Audio Analog Ground.
VCM I ADC Common Mode Reference(CMR) buffer output.CMR is approximately
2.25V.Bypass to analog ground with 47µF electrolytic in parallel with 0.1µF.
VREFP I DAC and ADC maximum reference.
Bypass to VCMR with 10µF in parallel with 0.1µF.
VCCAA I Analog VCC, 5V.
O Right channel output.
O Left channel input.
MIC1 I Microphone input 1.
MIC2 I Microphone 2.
VREF I Internal resistor divider generates Common Mode Reference(CMR) voltage.
Bypass to analog ground with 0.1µF.
VREFM I DAC and ADC minimum reference.
Bypass to VCMR with 10µF in parallel with 0.1µF.
RSET I Full scale DAC current adjustment.
COMP I Compensation pin.
VSSAV I Video Analog Ground
CDAC O Modulates chrominance output.
VCCAV I Video VCC, 5V
YDAC O Y Iuminance data bus for screen video port.
VDAC O Composite video output.
ACAP I Audio CAP.
XOUT O Crystal output.
XIN I 27 MHz crystal input.
PCLK I/O 13.5 MHz pixel clock.
I/O 27 MHz(2 times pixel clock).
O Horizontal sync(active-low).
O Vertical sunc(active-low).
I YUV data bus for screen video port.
Function
SEL_PLL0 DCLK
0 Bypass PLL(input mode)
0 27 MHz(output mode)
0 32.4 MHz(output mode)
1 40.5 MHz(output mode)
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