Philips 19PFL5522D Service Manual page 97

Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.11.11 Diagram TT, Type THC63LVD824 (IC2), LVDS Receiver
Block Diagram
1st Link
(25 to 135MHz)
2nd Link
(25 to 85MHz)
Pin Configuration
LVDS GND
RA1-
RA1+
RB1-
RB1+
LVDS VCC
RC1-
RC1+
RCLK1-
RCLK1+
RD1-
RD1+
LVDS GND
RA2-
RA2+
RB2-
RB2+
LVDS VCC
RC2-
RC2+
RCLK2-
RCLK2+
RD2-
RD2+
LVDS GND
LVDS INPUT
RA1 +/-
RB1 +/-
RC1 +/-
RD1 +/-
RCLK1 +/-
RA2 +/-
RB2 +/-
RC2 +/-
RD2 +/-
RCLK2 +/-
R/F
/PDWN
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Figure 9-22 Internal block diagram and pin configuration
8
8
28
8
PLL
8
28
8
8
PLL
LC7.2E LB 9.
CMOS/TTL OUTPUT
RED1
GREEN1 1st DATA
BLUE1
HSYNC
VSYNC
DE
RECEIVER CLOCK OUT
(25 to 85MHz)
RED2
GREEN2 2nd DATA
BLUE2
50 R15
49 GND
48 VCC
47 R14
46 R13
45 R12
44 R11
43 R10
42 GND
41 VCC
40 CLKOUT
39 B27
38 B26
37 B25
36 B24
35 B23
34 GND
33 VCC
32 B22
31 B21
30 B20
29 G27
28 GND
27 VCC
26 G26
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