Yamaha HTY-7040 Service Manual page 86

A B C
YSP-4000/YSP-40D/HTY-7040
INPUT 2/2
1
INPUT 1/2 BLOCK DIAGRAMS
IC22: LC72722PM
RDS signal processor
1 5 6
VDDA 3 CLOCK 14 VDDD
PLL
RECOVERY
REFERENCE (57 kHz)
(1187.5 Hz)
VOLTAGE
VSSA 4 15 VSSD
VREF
2
57 kHz
MPX IN ANTIALIASING SMOOTHING DATA
2 bpf 19 RDS-ID
FILTER FILTER DECODER
(SCF)
DO 20
CL 21 18 SYNC
RAM ERROR CORRECTION SYNC / EC
IC24, 32: TC7SH08FU
DI 22 CCB (24 BLOCK DATA) (SOFT DECISION) CONTROLLER
24 SYR
CE 23
2-input AND gate
CLK (4.332 MHz)
T1
7 MEMORY
T2 CONTROL
8 TEST SYNC SYNC
T3 DETECT-1 DETECT-2
9 OSC/DIVIDER
T4 10 IN B
IN A
11 16 17 13 12
GND
IC30: M3087BFKBGP
Microprocessor
3
8 8 8 8 8 8 8
Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 IC26: TC74VHCT08AFT
< (3) > < (3) >
V CC2 V CC1 Quad 2-input AND gate
Peripheral Functions
A/D Converter: Clock Generation Circuit
1 circuit X - X
IN OUT
X - X 1A
Timer (16-bit) Standard: 10 inputs CIN COUT
Timer A: 5-channel (2)
Maximum: 34 inputs On-chip Oscillator
Timer B: 6-channel 1B
PLL Frequency Synthesizer
UART/Clock Synchronous Serial I/O:
Three-Phase Motor Control Circuit 1Y
5-channel DMAC
2A
Watchdog Timer (15-bit) X/Y Converter: DMACII
16-bit x 16-bit
2B
CRC Calculation Circuit (CCITT):
D/A Converter:
16 12 5 2Y
8-bit x 2-channel CAN Module: 1-channel X +X +X +1
GND
M32C/80 series microprocessor core
Memory
Intelligent I/O
R0H R0L FLG
4 INTB ROM
R1H R1L
Time Measurement: 8-channel
R2
Waveform Generating: 8-channel ISP
Communication Functions:
R3 USP RAM
Clock Synchronous Serial I/O, UART,
HDLC Data Processing A0 PC
A1 SVF
FB SVP
Multiplier
SB VCT
< >
V (3) < V (3) >
CC1 CC2
Port P14 Port P15 Port P11 Port P12 Port P13 IC29: TC74VHCT245AFT
Octal bus transceiver
7 8 5 8 8
DIR 1
(Note 1)
NOTES: A1 2
1. Ports P11 to P15 are provided in the 144-pin package only.
2. Included in the 144-pin package only.
A2 3
3.The supply voltage of M32C/84T (High-reliability version) must be V CC1 =V CC2 .
A3 4
A4 5
5
IC31: BR25L320F-W EEPROM
A5 6
SPI BUS 32 k-bits (4,096 x 8-bit) EEPROM
A6 7
A7 8
1 8 Vcc
CS VOLTAGE A8 9
INSTRUCTION DECODE DETECTION
CONTROL CLOCK GND 10
GENERATION
WRITE HIGH VOLTAGE
SO 2 INHIBITION GENERATOR 7 HOLD
INSTRUCTION
REGISTER
STATUS REGISTER
3 6 SCK
WP
ADDRESS ADDRESS
12bit 12bit
REGISTER DECODER
32,768bit
EEPROM
DATA READ/WRITE
8bit 8bit
REGISTER AMP
GND 4 5 SI
6
IC37: AD8056AR
IC33: TC74LCX245FT
Voltage feedback amplifiers
Low voltage octal bus transceiver with 5-V tolerant inputs and outputs
OUT 1
DIR 1 20 Vcc 1
A1 2 19 OE
–IN 1 2
A2 3 18 B1
+IN 1 3
A3 4 17 B2
–V 4
S
A4 5 16 B3
A5 6 15 B4
7 A6 7 14 B5
A7 8 13 B6
A8 9 12 B7
GND 10 11 B8
IC35: TA1318AF
SYNC processor, frequency counter IC for TV component signals
DAC3 D2-OUT VD1-OUT NC SYNC1-IN DAC1 SYNC2-IN Address SW SCL SDA NC HD2-OUT Digital GND
30 29 28 27 26 25 24 23 22 21 20 19 18
2
DAC3 INV INV SYNC DAC1 SYNC I CBUS INV
SW SW SW SEPA SW SEPA Decoder SW
TEST DAC3 DAC1
DV2-OUT DV1-OUT HD2-OUT
8
SW SW SW
V-Input V-FREQ
V C/D
SW SW
H/V-
V-FREQ
FREQ
Counter V-SYNC DET SW
Clamp
CP
Pulse SW
DAC2
DAC2 V HD
H/
2 u f H
SYNC SW Integral Polarity
H-FREQ H-INPUT
H-AFC H C/D H-Ramp
DET SW SW
H-FREQ
HVCO
SW
9
1 2 3 4 5 6 7 8 9 10 11 12 13
HD2-IN VD2-IN HD1-IN VD1-IN Analog GND NC AFC Filter NC HVCO NC V DAC2 VD3-IN
CC
# All voltages are measured with a 10MΩ/V DC electronic voltmeter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
10
86
D E F
1 5 V CC
2
3 4 OUT Y
1 14 Vcc
2 13 4B
3 12 4A
4 11 4Y
5 10 3B
6 9 3A
7 8 3Y
20 Vcc
19 G
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
8 +V
S
7 OUT
+ – + –
6 –IN 2
5 +IN
2
NC HD1-OUT
17 16
INV
SW
HD1-OUT
SW
14 15
HD3-IN CP-OUT
G H I J K L M N