Memory; M24C16-Bng - Hitachi 36SDX88B Service Manual

4. Memory
4.1 Memory
M24Cl6-BNG
The memory is an electrically erasable programmable
memory (EEPROM) fabricated with High Endurance
Single Polysilicon CMOS technology which guarantees
an endurance typically well above one million erase/
write cycles with a
data
retention of 40 years.
Table I. Signal Names
r EKE2
1 Chip Enable Inputs
1 SDA 1 Serial Data Address InautlOutput 1
I
SCL I Serial Clock
I
WC
I Write Control
vcc
vss
Supply Voltage
Ground
Figure I. Logic Diagram
EO-E2
SCL
M24Cxx
vss
- SDA
The memory is compatible with the 1% standard, two
wire serial interface which uses a bi-directional data
bus
and serial clock. The memory carry a built-in 4 bit
unique Device Type lndentifier code (1010) which
corresponds to the 1*C bus definition. The Device Type
Identifier code is used together with 3 Chip Enable bits.
Depending on the size of the device memory, these
Chip Enables bits can be directly linked to the EO-El-
E2 input pins or can be used as Most Significant Address
bits for the memory area. The l*C protocol allows to
address up to 16K bits of memory on the same bus.
Using the EO-El-E2 inputs pins.
The memory behaves as a slave device in the l*C
protocol with all memory operations synchronized by
the serial clock. Read and write operations are initiated
by
a START condition generated by the bus master.
The START condition is followed by the Device Select
Code which
is
composed by a stream of 7 bits (Device
Type Identifier code '1010 followed by the 3 Chip Enable
bits), plus one read/write bit (R w> and terminated by
acknowledged bit.
When writing data to the memory, it responds to the 8
bits received by asserting an acknowledge bit during
the 9th bit time. When data is read
by
the bus master,
it acknowledges the receipt of the data bytes in the
same way. Data transfers are terminated with a STOP
condition after an Ack for WRITE and after a No Ack
for READ.
Power On Reset: Vcc lock out write protect. In order
to prevent any possible data corruption and inadvertent
write operations during power up, a Power On Reset
(POR) circuit is implemented. Until the Vcc voltage
has reached the POR threshold value, the internal reset
is active, all operations are disabled and the device will
not respond to any command. In the same way, when
Vcc drops down from the operating voltage to below
the POR threshold value, all operations are disabled
and the device will not respond to any command. A
stable V,, must be applied before applying any logic
signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of memory. A resistor
can be connected from the SCL line to Vcc to act as a
pull up.
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