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IC BLOCK DIAGRAM & DESCRIPTION
IC701 LC587008 (4bit MICON)
Function
Pin No.
V
24
DD
Power supply
V
23
SS
LCD drive power supply
NON
1/1 bias
V
1
22
DD
VDD
V
2
21
DD
VDD1
VDD2
VSS
Switching pin used to supply the LCD drive voltage to the VDD1 and
V
2 PINS
DD
CUP1
3
Connect a nonpolarized capacitor between CUP1 and CUP2 when
CUP2
4
1/2 or 1/3 bias is used
Leave open when a bias other than 1/2 or 1/3 is used.
System clock oscillator connections
Input
CFIN
25
Ceramic resonator connection (CF specifications)
RC component connection (RC specifications)
External signal input pin (CFOUT is left open)
26
This oscillator is stopped by the execution of aSTOP or SLOW
Output
CFOUT
instruction.
Referenc e calculation(cl ock specification s,LCD alternain g frequency),
XTIN
Input
20
system clock oscillator
32 kHz crystal resonator connection
65 kHz crystal resonator connection
Output
19
XTOUT
This oscillator is stopped by the execution of aSTOP instruction.
Input-only ports
S1
27
Input pins used to read data into RAM
Built-in 7.8 ms and 1.95 ms chatter rejection circuits
S2
28
Input
S3
Built-in pull-up/pull-down resistors
29
Note: The 7.8 ms and 1.95 ms times are the times when f 0 is
S4
30
32.768kHz.
I/O ports
Input pins used to output read data into RAM
K1
31
Output pins used to output data from RAM
K2
32
I/O
Built-in 7.8 ms and 1.95 ms input-mode chatter rejection circuits.
33
K3
The selection of 7.8 or 1.95 ms is linked to that for the S ports.
K4
34
Note: The 7.8 ms and 1.95 ms times are the times when f 0 is
32.768 kHz.
I/O ports
M1
35
Input pins used to read data into RAM
Output pins used to output data from RAM
M2
36
I/O
M4 is used as the external clock input pin in Tm2 mode 3.
M3
37
*The minimum period for the external clock is twice the cycle time.
M4
38
Built-in pull-up/pull-down resistors
11
A1
I/O ports
12
Input pins used to read data into RAM
A2
I/O
A3
13
Output pins used to output data from RAM
14
Built-in pull-up/pull-down resistors
A4
P1
15
I/O ports
P2
16
I/O
17
Function: The same as pins A1 to A4
P3
18
P4
Option
At reset
1/2 bias
1/3 bias
CF specifications
RC specifications
External
Specifications
Not used
32k specifications
65k specifications
38k specifications
Not used
The pull-up or pull-
Transistor to hold
down resistor are
a low or high level
on.
Selection of either
Note:
These pins go
pull-up or pull-
to the floatin g
down resistor
sta te when
res et is cleare d.
The pull-up or pull-
down resistors are
on.
Transistors to hold
Note:
The se pins go
a low or high level
to the floatin g
Selection of either
sta te when
pull-up or pull-
res et is cleare d.
down resistor
Input mode
Outpu t latch data is
set high.
The same as K1 to
The same as K1 to
K4
K4
The same as K1 to
The same as K1 to
K4
K4
The same as K1 to
The same as K1 to
K4
K4
Continued from preceding page.
QIP-80
Pin
I/O
Pin No.
I/O ports
Function: The same as for pins A1 to A4
Pins So1 to So3 area also used for the serial interface.
So1
7
Use of these pins inserial mode can be selected under program
So2
8
cotrol.
I/O
So3
9
Pin functions: SO1:Serial input pin
So4
10
SO2:Serial output pin
SO3:Serial clock pin
The serial clock pin can be switched between internal and external,
and between rising edge output and falling edge output.
Output-only ports
Output pins used to output data from RAM
N1
39
An alarm signal can be output from pin N4.(Note that this is only
N2
40
when the N4 output latch is low.)
Output
N3
41
An alarm signal modulated at 1,2 or 4 kHz can be output.(These
N4
42
frequencies are output when f 0 is 32.768 kHz.)
A carrier signal can be output from N3.(Note that this is only
when the N3 output latch is low.)
Input ports
External interrupt request inputs
INT
6
Input pins used to read data into RAM
Input
Input detection can be performed on either rising or falling edges.
Built-in pull-up/pull-down resistors
LSI internal reset input
The reset input level can be selected to be either high or low.
RES
5
Input
Built-in pull-up/pull-down resistors
Note: The reset pulse must be at least 500us.
Test input
TST
Input
43
QIP80 products: Connect to Vss.
Chip products : Leave open or connect to Vss.
LCD panel drive/general-purpose output
LCD panel drive
STATIC
1/2 bias-1/2 duty
1/2 bias-1/3 duty
1/2 bias-1/4 duty
1/3 bias-1/3 duty
1/3 bias-1/4 duty
Types I to V can be specified as mask options.
Seg1,
44,
General-purpose output mode
Seg2 to
Output
45 to
CMOS
Seg35
78
P-channel open drain
N-channel open drain
Types I to III can be specified as mask options.
LCD/g eneral -purpo se output contro l is handle d by the segme nt PLA,
and thus program control is not required.
These pins support output latch control on reset and in standby
states when the oscillators are stopped.
Arbit rary combinat ions of LCD drive and gene ral-p urpos e output s can
be used.
LCD panel drive common polarity outputs
The table below shows how these pins are used depen ding on the duty
used.( values for alterna ting freque ncy reflect a typical specif ication of
32.768 MHz for f 0.)
Static duty
COM1
2
COM2
1
COM1
Output
COM3
80
COM2
COM4
79
COM3
COM4
Alternation
32 Hz
32 Hz
frequency
Note: A cross( X ) indicates that the pin is not used with that duty type.
- 8 -
Function
Option
Tra nsis tors to hold
a low or high leve l
Sel ecti on of eith er
pull -up or pull-
dow n resis tors
The same as for K1
Inte rna l seria l clock
to K4
divi sor selecti on
I
1/1
II
1/2
III
1/4
Pins N1 to N4
outpu t circuit type:
The outp ut level s on
pins N1 to N4 can be
spec ified as an opti on
Pins N1 to N4
output level
Tran sistors to hold
a low or high level
Select ion of either
pull-up or pull-
down resist ors
Signal convers ion
(rising/f alling)
selectio n
*Onl y when the
inpu t resisto r open
spec ificat ion is
selec ted
LCD driver/
LCD drive
general-purpose
output switching
LCD drive type
*:Determined by
switching
mask options
STATIC
General purpose
1/2 bias-1/2
outputs
duty
1/2 bias-1/3
duty
1/2 bias-1/4
duty
Note:When a
1/3 bias-1/3
duty
1/3 bias-1/4
duty
General-purpose
output circuit
switching
CMOS
P-channel
open drain
These pins go to
N-channel
the static drive
open drain
mode during the
Outpu t latc h con trol
reset period.
in standb y mode s
The static drive
waveform is output
during the reset
period.
*There are cases
1/2 duty
1/3 duty
1/4 duty
where the
alternati ng
frequenc y stops for
the CF,RC and
external clock
specifica tions.
(These cases differ
32 Hz
42.7 Hz
32 Hz
dependi ng on option
specifica tions.)
At reset
All segment s on
All segments off
High level
Low level
Determined by
mask options
comb inatio n of
LCD drive and
gene ral-
purpo se
outpu ts,the
outpu t state is
eithe r:
All lit/hig h level
All off/low level.
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