Sharp LC-26SH7E/RU Service Manual page 104

LC-19SH7E/RU, LC-26SH7E/RU, LC-32SH7E/RU, LC-42SH7E/RU
1.8. U391 (NAND128W3A2BN6E)
FEATURES
· HIGH DENSITY NAND FLASH MEMORIES
– Up to 1 Gbit memory array
– Up to 32 Mbit spare area
– Cost effective solutions for mass storage applications
· NAND INTERFACE
– x8 or x16 bus width
– Multiplexed Address/ Data
– Pinout compatibility for all densities
· SUPPLY VOLTAGE
– 1.8V device: VDD = 1.7 to 1.95V
– 3.0V device: V = 2.7 to 3.6V
DD
· PAGE SIZE
– x8 device: (512 + 16 spare) Bytes
– x16 device: (256 + 8 spare) Words
· BLOCK SIZE
– x8 device: (16K + 512 spare) Bytes
– x16 device: (8K + 256 spare) Words
· PAGE READ / PROGRAM
– Random access: 12µs (max)
– Sequential access: 50ns (min)
– Page program time: 200µs (typ)
· COPY BACK PROGRAM MODE
– Fast page copy without external buffering
· FAST BLOCK ERASE
– Block erase time: 2ms (Typ)
· STATUS REGISTER
· ELECTRONIC SIGNATURE
· CHIP ENABLE 'DON'T CARE' OPTION
– Simple interface with microcontroller
· SERIAL NUMBER OPTION
· HARDWARE DATA PROTECTION
– Program/Erase locked during Power transitions
· DATA INTEGRITY
– 100,000 Program/Erase cycles
– 10 years Data Retention
· RoHS COMPLIANCE
– Lead-Free Components are Compliant with the RoHS Directive
· DEVELOPMENT TOOLS
– Error Correction Code software and hardware models
– Bad Blocks Management and Wear Leveling algorithms
– File System OS Native reference software
– Hardware simulation models
The NAND Flash 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that uses the Single Level Cell (SLC) NAND cell technology. It is
referred to as the Small Page family. The devices range from 128Mbits to 1Gbit and operate with either a 1.8V or 3V voltage supply. The size of a Page is
either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the Data In-put/Output signals on a multiplexed x8 or x16 In-put/Output bus. This interface reduces the pin count
and makes it possible to migrate to other densities without changing the footprint.
Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is strongly recommended to implement
an Error Correction Code (ECC). A Write Protect pin is available to give a hardware protection against program and erase operations.
The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active. The
use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor.
A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed
in another page without having to resend the data to be programmed.
The devices are available in the following packages:
· TSOP48 12 x 20mm for all products
· WSOP48 12 x 17 x 0.65mm for 128Mb, 256Mb and 512Mb products
· VFBGA55 (8 x 10 x 1mm, 6 x 8 ball array, 0.8mm pitch) for 128Mb and 256Mb products
· TFBGA55 (8 x 10 x 1.2mm, 6 x 8 ball array, 0.8mm pitch) for 512Mb Dual Die product
· VFBGA63 (8.5 x 15 x 1mm, 6 x 8 ball array, 0.8mm pitch) for the 512Mb product
· TFBGA63 (8.5 x 15 x 1.2mm, 6 x 8 ball array, 0.8mm pitch) for the 1Gb Dual Die product Two options are available for the NAND Flash family:
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