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Freescale Semiconductor MC13192 Reference Manual

2.4 ghz low power transceiver for the ieee 802.15.4 standard
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MC13192
2.4 GHz Low Power Transceiver
for the IEEE
802.15.4 Standard
®
Reference Manual
Document Number: MC13192RM
Rev. 1.6
04/2008

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Summary of Contents for Freescale Semiconductor MC13192

  • Page 1 MC13192 2.4 GHz Low Power Transceiver for the IEEE 802.15.4 Standard ® Reference Manual Document Number: MC13192RM Rev. 1.6 04/2008...
  • Page 2 Technical Information Center Schatzbogen 7 support or sustain life, or for any other application in which the failure of the Freescale Semiconductor 81829 Muenchen, Germany product could create a situation where personal injury or death may occur. Should Buyer purchase...

  • Page 3: Table Of Contents

    MC13192 Interface to MCU........
  • Page 4 MC13192 Digital Signal Properties Summary ........
  • Page 5 Low Power Modes ............6-4 MC13192 Reference Manual, Rev. 1.6...
  • Page 6 Stream Mode Timer_Triggered TX or RX Events ......7-7 MC13192 Reference Manual, Rev. 1.6...
  • Page 7 Input Pin ATTN ............. 9-6 MC13192 Reference Manual, Rev. 1.6...
  • Page 8 MC13192 Reference Manual, Rev. 1.6 viii Freescale Semiconductor...

  • Page 9: Audience

    About This Book This manual describes the Freescale MC13192. The MC13192 is a 2.4 GHz ISM band transceiver built for the 802.15.4 Standard. The MC13192 transceiver can function as a standalone transceiver or when combined with a software package and an HCS08 MCU, they form the Freescale 802.15.4 Standard platform solution.

  • Page 10: Revision History

    Full Function Device Coordinator Frame Length Indicator Guaranteed Time Slot Hardware Interrupt Request Interrupt Service Routine Local Oscillator Medium Access Control MCPS MAC Common Part Sublayer Microcontroller Unit MLME MAC Sublayer Management Entity MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 11: References

    Start of Frame Delimiter Serial Peripheral Interface SSCS Service Specific Convergence Layer Software Voltage Controlled Oscillator References The following sources were referenced to produce this book: ® [1] IEEE 802.15.4 Standard [2] Freescale MC13192 Data Sheet MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...
  • Page 12 MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 13: Introduction

    Chapter 1 Introduction The MC13192 is a short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers. The MC13192 contain a complete 802.15.4 Standard physical layer (PHY) modem designed for the 802.15.4 Standard which supports peer-to-peer, star, and mesh networking.

  • Page 14: Features

    — Meets moisture sensitivity level (MSL) 3 — 260°C peak reflow temperature — Meets lead-free requirements Software Support Freescale provides a wide range of software functionality to complement the MC13192 hardware. There are three levels of application solutions: • Simple proprietary wireless connectivity •...

  • Page 15: Simple Mac (Smac)

    Advanced Encryption Standard (AES) 128-bit security Block Diagrams Figure 1-1 shows a simplified block diagram of the MC13192 which is an 802.15.4 Standard compatible transceiver that provides the functions required in the physical layer (PHY) specification. V D D A...

  • Page 16: Data Transfer Modes

    Packet Structure Figure 1-3 shows the packet structure of the MC13192. Payloads of up to 125 bytes are supported. The MC13192 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A Frame Check Sequence (FCS) is calculated and appended to the end of the data.

  • Page 17: Receive Path Description

    64 µs period after the packet preamble and stored in RAM. If the MC13192 is in Packet Mode, the data is processed as an entire packet. The MCU is notified that an entire packet has been received via an interrupt.
  • Page 18 Introduction MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 19: Mc13192 Pins And Connections

    Chapter 2 MC13192 Pins and Connections Device Pin Assignment RFIN- GPIO6 RFIN+ GPIO5 VDDINT VDDD PAO+ MC13192 PAO- MISO GPIO4 MOSI Figure 2-1. MC13192 Pinout MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 20: Pin Definitions

    After sequence is complete, return RXTXEN to low. When held low, forces Idle Mode. ATTN Digital Input Active Low Attention. Transitions IC from either Hibernate or Doze Modes to Idle. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...
  • Page 21 VDDLO1 Power Input LO1 VDD supply. Connect to VDDA externally. VDDVCO Power Output VCO regulated supply bypass. Decouple to ground. VBATT Power Input Analog voltage regulators Input. Decouple to ground. Connect to Battery. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...
  • Page 22 Connect to directly VDDLO1 and VDDLO2 externally and to PAO± through a frequency trap. Note: Do not use this pin to supply circuitry external to the chip. Ground External paddle / flag ground. Connect to ground. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 23: System Considerations

    System Considerations Introduction The MC13192 is the embodiment of an 802.15.4 Standard transceiver in a single QFN package which can provide solutions to proprietary nets, 802.15.4 Standard MAC-compatible nets, or full ZigBee-compatible nets. All control to the modem is through the common SPI bus, the MCU interrupt request, and several MCU GPIO lines.

  • Page 24: Test Pin Sm

    VDDD 100 nF VDDVCO 100 nF Figure 3-1. MC13192 Power Supply Connections NOTE There are separate bypass capacitors on VDDA, VDDD, and VDDVCO. In some RF circuitry configurations, VDDA may also need to be DC-coupled to the radio PA outputs.

  • Page 25: Mc13192 Interface To Mcu

    Modem MISO output drives MCU MISO1. • MCU SPSCK1 output drives modem SPICLK. • MCU SS1 output drives modem CE. The use and programming of the SPI command channel is described in Chapter 5, “Serial Peripheral Interface (SPI). MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 26: Interrupt Request To Mcu

    <9 pF. The oscillator needs to see a balanced load capacitance at each terminal of about 18pF. As a result, the sum of the stray capacitance of the PCB, device pin (XTAL1 or XTAL2), and load MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 27: System Clock Configurations

    As described in Section 9.3.2, “Crystal Trim Operation, the MC13192 crystal oscillator frequency can be trimmed by programming modem CLKO_Ctl Register 0A, Bits 15-8 (xtal_trim[7:0]). The trimming procedure varies the frequency by a few hertz per step, depending on the type of crystal. As xtal_trim[7:0] is increased, the frequency is decreased.

  • Page 28: Single System Crystal With Clko Driving Mcu Crystal Input

    Signals, GPIO1 and GPIO2 can be programmed as special status signals. The alternate functionality of the GPIO1-GPIO2 are controlled by the applications program and use of these pins is described in Chapter 9, “Miscellaneous Functions. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 29: Mc13192 Digital Signal Properties Summary

    Functions. MC13192 Digital Signal Properties Summary Table 3-2 summarizes digital I/O pin characteristics. These characteristics are determined by the way the common pin interfaces are hard-wired to internal circuits. Table 3-2. MC13192 Digital Signal Properties High Current Output Pull-Up Comments...

  • Page 30: Transceiver Rf Port Operation And External Connections

    System Considerations Transceiver RF Port Operation and External Connections The MC13192 radio has features that allow for a flexible as well as low cost RF interface: • Programmable output power - 0 dBm nominal output power, programmable from -27 dBm to +3 dBm typical •...

  • Page 31: Low Power Considerations

    Over-the-air operation uses RX, TX, and CCA modes, where power is highest. As a result, the time between radio operations should be kept at the longest possible period that the application will allow. When designing low power operation of the MC13192 consider: •...

  • Page 32: Modem Low Power States

    Doze, and the CLKO output can be kept active in Doze to provide a clock to the MCU. Doze uses considerable more current than Off or Hibernate. RAM and register data are retained and digital I/O retain their state. Table 3-3. MC13192 Modem Low Power States Current Mode...

  • Page 33: Special Considerations For Hibernate And Doze Low Power Modes

    To work around this issue, there are three choices: 1. Prevent the application from asserting ATTN during this period. As an example, for an End Node that is sleeping for long periods, this would present no problems. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor 3-11...

  • Page 34: Recovery Times From Low Power Modes

    Doze, or an interrupt will be asserted for exiting Doze Mode via a timer. IDLE 500µA 10 - 25ms (300+1/CLKO)ms DOZE 35µA 8 - 20ms HIBERNATE 0.2µA 1µA Figure 3-4. MC13192 Modem Low Power Recovery Times MC13192 Reference Manual, Rev. 1.6 3-12 Freescale Semiconductor...

  • Page 35: 3.10.3.1 Modem Active Currents

    (CCA), RX, and TX, and each has a separate current profile. Table 3-4 lists the typical currents while in the listed modes, but does not show the transition profiles when moving between modes. Table 3-4. MC13192 Active State Currents Mode Current (typ @ 2.7V) 500 μA...

  • Page 36: Modem Rx Timing Profile

    10 μs to allow the RF transmitter to taper off in a manner to avoid RF “splatter”. State: Idle Warmup Idle Warm down 144 μs 10 μs Figure 3-7. TX Timing Profile MC13192 Reference Manual, Rev. 1.6 3-14 Freescale Semiconductor...

  • Page 37: General System Considerations For Low Power

    The default condition is for MISO to go to tristate when CE is de-asserted. Program Control_B Register 07, Bit 11, miso_hiz_en = 0 so MISO will be driven low when CE is de-asserted. As a result MISO will not float when Doze or Hibernate Mode is enabled. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor 3-15...
  • Page 38 System Considerations MC13192 Reference Manual, Rev. 1.6 3-16 Freescale Semiconductor...

  • Page 39: Spi Register Descriptions

    SPI Register Descriptions Overview All control, reading of status, writing of data, and reading of data is done through the MC13192 SPI port. The host microcontroller accesses the transceiver through SPI “transactions” in which multiple bursts of byte-long data are transmitted on the SPI bus. Each transaction is three or more bursts long depending on the transaction type, and these are described in detail in Section 5.2.2, “SPI Burst...

  • Page 40: Register Model And Description Details

    SPI Register Descriptions Register Model and Description Details Table 4-2 summarizes the MC13192 Register Model and the following sections describe each register in more detail. Table 4-2. MC13192 SPI Register Table REGISTER NAME (Hex) Reset software_reset RX_Pkt_RAM rx_pkt_ram[15:0] TX_Pkt_RAM tx_pkt_ram[15:0]...
  • Page 41 SPI Register Descriptions Table 4-2. MC13192 SPI Register Table (continued) REGISTER NAME (Hex) GPIO_Dir GPIO_Data_Out LO1_Int_Div lo1_idiv[7:0] LO1_Num lo1_num[15:0] PA_Lvl Tmr_Cmp1_A tmr_cmp1[23:16] Tmr_Cmp1_B tmr_cmp1[15:0] Tmr_Cmp2_A tmr_cmp2[23:16] Tmr_Cmp2_B tmr_cmp2[15:0] Tmr_Cmp3_A tmr_cmp3[23:16] Tmr_Cmp3_B tmr_cmp3[15:0] Tmr_Cmp4_A tmr_cmp4[23:16] Tmr_Cmp4_B tmr_cmp4[15:0] TC2_Prime tc2_prime[15:0] MC13192 Reference Manual, Rev. 1.6...
  • Page 42 SPI Register Descriptions Table 4-2. MC13192 SPI Register Table (continued) REGISTER NAME (Hex) IRQ_Status RST_Ind Current_Time_A et[23:16] Current_Time_B et[15:0] GPIO_Data_In Chip_Id chip_id[8:0] RX_Status cca_final[7:0] rx_pkt_latch[6:0] Timestamp_A timestamp[23:16] Timestamp_B timestamp[15:0] BER_Enable PSM_Mode psm_tm[2:0] MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 43: Reset - Register 00

    RX_Pkt_RAM - Register 01 The receive Packet RAM register is accessed when the MC13192 is being used in Packet Mode or Stream Mode for data transfer. In Packet Mode once a packet has been received, the payload data is stored in the RX Packet RAM and the length of the packet data is contained in Register 2D, Bit 6-0.

  • Page 44: Tx_Pkt_Ram - Register 02

    TX_Pkt_RAM - Register 02 The transmit Packet RAM register is accessed when the MC13192 is being used in Packet Mode or Stream Mode for data transfer. There are two transmit Packet RAMs and only one is accessed when the MC13192 is being used in Packet Mode for data transfer.

  • Page 45: Tx_Pkt_Ctl - Register 03

    Bits 6 - 0 tx_pkt_length[6:0] — The Transmit Packet Length bits represent the number Total transmit payload data of bytes to be transmitted from transmit Packet RAM plus 2 bytes for FCS. length in bytes MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 46: Cca_Thresh - Register 04

    - Threshold value for Clear Channel Assessment in dB-linear format Default is 0x00. Bits 7-0 power_comp[7:0] - This is a binary value that is added to the measured value of the Default is 0x8D CCA operation. The result is stored in cca_final[7:0] MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 47: Irq_Mask - Register 05

    The IRQ_Mask Register 05 provides most, but not all, mask bits for various interrupt sources for the MC13192. If a mask bit is set, its associated status bit being true will generate an interrupt on the MC13192 IRQ pin. The interrupt is cleared when the status bit is read via a SPI transaction.
  • Page 48 Operation Bit 8 acoma_en — The Acoma Mode enable bit controls Doze Mode. 1 = The MC13192 stays in Doze until Acoma is an enhanced power save mode within Doze. ATTN asserted. Event Timer and Prescaler clocks disabled for additional current savings.

  • Page 49: Control_A - Register 06

    SPI Register Descriptions 4.10 Control_A - Register 06 The Control_A Register 06 is one of several registers that provide control fields for the MC13192. Register 06 0x06 TYPE r/w r/w r/w r/w r/w r/w RESET 0x0010 Table 4-9. Register 06 Description...
  • Page 50 — The transceiver operation bits select one of four 00 = Idle (default) possible transceiver modes. 01 = CCA /energy detection 10 = Packet Mode RX 11 = Packet Mode TX MC13192 Reference Manual, Rev. 1.6 4-12 Freescale Semiconductor...

  • Page 51: Control_B - Register 07

    SPI Register Descriptions 4.11 Control_B - Register 07 The Control_B Register 07 is one of several registers that provide control fields for the MC13192. Register 07 0x07 TYPE r/w r/w r/w RESET 0x0C00 Table 4-10. Register 07 Description Name Description...

  • Page 52: Pa_Enable - Register 08

    0 = Packet Mode 1 = Stream Mode Bit 1 hib_en — The hibernate enable bit can set the MC13192 into its 1 = Places the MC13192 into its lowest power lowest power saving mode without a running time base.

  • Page 53: Control_C - Register 09

    SPI Register Descriptions 4.13 Control_C - Register 09 The Control_C Register 09 is one of several registers that provide control fields for the MC13192. Register 09 0x09 TYPE RESET 0xF36B Table 4-12. Register 09 Description Name Description Operation Bits 15-8, 6,...

  • Page 54: Clko_Ctl - Register 0A

    4.14 CLKO_Ctl - Register 0A The MC13192 provides the ability to trim the crystal oscillator frequency and an output clock with a programmable frequency that can be used to drive another device, such as a microcontroller. The field xtal_trim[7:0], CLKO_Ctl Register 0A, Bits 15-8, alter the capacitive loading to the crystal and affects the oscillator frequency.

  • Page 55: Gpio_Dir - Register 0B

    1 = GPIO7 enabled as input. 0 = GPIO7 disabled as input. Bit 5 gpio6_ien— This bit configures GPIO6 as an input. 1 = GPIO6 enabled as input. 0 = GPIO6 disabled as input. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor 4-17...
  • Page 56 1 = GPIO2 enabled as input. 0 = GPIO2 disabled as input. Bit 0 gpio1_ien— This bit configures GPIO1 as an input. 1 = GPIO1 enabled as input. 0 = GPIO1 disabled as input. MC13192 Reference Manual, Rev. 1.6 4-18 Freescale Semiconductor...

  • Page 57: Gpio_Data_Out - Register 0C

    — GPIO4 output value. 1 = GPIO4 driven high 0 = GPIO4 driven low Bit 2 gpio3_o — GPIO3 output value. 1 = GPIO3 driven high 0 = GPIO3 driven low MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor 4-19...

  • Page 58: Lo1_Int_Div - Register 0F

    Operation Bits 15-8 Reserved. Leave default. Bits 7-0 lo1_idiv[7:0] — The LO1 integer divide bits represent the integer Default is 149dec (0x95). See Table 4-19. divide value for the LO1 fractional-N synthesizer. MC13192 Reference Manual, Rev. 1.6 4-20 Freescale Semiconductor...

  • Page 59: Lo1_Num - Register 10

    152 / 0x98 49152 / 0xC000 2465 153 / 0x99 4096 / 0x1000 2470 153 / 0x99 24576 / 0x6000 2475 153 / 0x99 45056 / 0xB000 2480 154 / 0x9A 0 / 0x0000 MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor 4-21...

  • Page 60: Pa_Lvl - Register 12

    Bits 3-2 pa_drv_coarse[1:0] - These bits select the coarse PA drive level Leave default adjustment. Bits 1-0 pa_drv_fine[1:0] - These bits select the fine PA drive level adjustment Leave default MC13192 Reference Manual, Rev. 1.6 4-22 Freescale Semiconductor...

  • Page 61: Tmr_Cmp1_A - Register 1B

    The Tmr_CMP1_B Register 1C stores the least significant 16 bits of the 24-bit compare value. Writing to Register 1C causes an internal load of the full 24-bit comparator value (see Section 4.20, “Tmr_Cmp1_A - Register 1B) and activates the mode presently set into the tmr_cmp1_dis control bit. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor 4-23...
  • Page 62 Table 4-22. Register 1C Description Name Description Operation Bits 15-0 tmr_cmp1[15:0] — These bits represent the 16 least significant bits of Default is 0xFFFF. 24-bit Event Timer 1 absolute time compare value, tmr_cmp1[23:0]. MC13192 Reference Manual, Rev. 1.6 4-24 Freescale Semiconductor...

  • Page 63: Tmr_Cmp2_A - Register 1D

    The Tmr_CMP2_B Register 1E stores the least significant 16 bits of the 24-bit compare value. Writing to Register 1E causes an internal load of the full 24-bit comparator value (see Section 4.22, “Tmr_Cmp2_A - Register 1D) and activates the mode presently set into the tmr_cmp2_dis control bit. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor 4-25...
  • Page 64 Table 4-24. Register 1E Description Name Description Operation Bits 15-0 tmr_cmp2[15:0] — These bits represent the 16 least significant bits of Default is 0xFFFF. 24-bit Event Timer 2 absolute time compare value, tmr_cmp2[23:0]. MC13192 Reference Manual, Rev. 1.6 4-26 Freescale Semiconductor...

  • Page 65: Tmr_Cmp3_A - Register 1F

    The Tmr_CMP3_B Register 20 stores the least significant 16 bits of the 24-bit compare value. Writing to Register 20 causes an internal load of the full 24-bit comparator value (see Section 4.24, “Tmr_Cmp3_A - Register 1F) and activates the mode presently set into the tmr_cmp3_dis control bit. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor 4-27...
  • Page 66 Table 4-26. Register 20 Description Name Description Operation Bits 15-0 tmr_cmp3[15:0] — These bits represent the 16 least significant bits of 24-bit Default is 0xFFFF. Event Timer 3 absolute time compare value, tmr_cmp3[23:0]. MC13192 Reference Manual, Rev. 1.6 4-28 Freescale Semiconductor...

  • Page 67: Tmr_Cmp4_A -Register 21

    0 = Enables Event Timer Compare 4 function (default). Bits 7-0 tmr_cmp4[23:16] — These bits represent the 8 most significant bits of 24-bit Default is 0xFF. Event Timer 4 absolute time compare value, tmr_cmp4[23:0]. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor 4-29...
  • Page 68 Table 4-28. Register 22 Description Name Description Operation Bits 15-0 tmr_cmp4[15:0] — These bits represent the 16 least significant bits of 24-bit Event Default is 0xFFFF. Timer 4 absolute time compare value, tmr_cmp4[23:0]. MC13192 Reference Manual, Rev. 1.6 4-30 Freescale Semiconductor...

  • Page 69: Tc2_Prime - Register 23

    TC2_Prime - Register 23 When the MC13192 is used in Stream Mode (Register 7, Bit 5 = 1), the 16-bit TC2_Prime Register 23 is used in place of the 24-bit Tmr_Cmp2 register(s) to initiate timer-triggered sequences. For an interrupt to be generated, tmr2_mask must be set (value = 1) and the interrupt is generated via the tmr2_irq status.

  • Page 70: Irq_Status - Register 24

    SPI before the previous word is read. write error For TX Stream Mode, the current TX word transmission is complete prior to next TX word being written to SPI. MC13192 Reference Manual, Rev. 1.6 4-32 Freescale Semiconductor...
  • Page 71 The bit being set indicates the ATTN signal has been ATTN pin has been asserted or Power-up complete asserted low or that the MC13192 has reached a Power-up condition from a reset condition. complete condition after software reset (CE released) or a hardware reset (RST released).

  • Page 72: Rst_Ind - Register 25

    25 was read since the last RST assertion or program reset. RST or Program Reset event. 0 = Register 25 has not been read since the last RST or Program Reset event. Note: Reading Register 25 will set Bit 7. MC13192 Reference Manual, Rev. 1.6 4-34 Freescale Semiconductor...

  • Page 73: Current_Time_A - Register 26

    TYPE RESET 0x0000 Table 4-33. Register 27 Description Name Description Operation Bits 15-0 et[15:0] — These bits represent the 16 least significant bits of the current time of the Event Timer counter. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor 4-35...

  • Page 74: Gpio_Data_In - Register 28

    Bit 8 gpio1_i — This bit is the input value of GPIO1. With gpio1_oen = 0 and gpio1_ien = 1; GPIO1 is configured as an input whose value can be read from gpio1_i. MC13192 Reference Manual, Rev. 1.6 4-36 Freescale Semiconductor...

  • Page 75: Chip_Id - Register 2C

    Bits 6- 0 rx_pkt_latch [6:0] — RX packet length These bits give the RX packet length parsed from the packet header. The value is latched when an RX Start Frame Delimiter is detected. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor 4-37...

  • Page 76: Timestamp_A - Register 2E

    TYPE RESET 0x0000 Table 4-38. Register 2F Description Name Description Operation Bits 15-0 timestamp[15:0] — 16 least significant bits of the latched 24-bit timestamp value for the beginning of the receive packet. MC13192 Reference Manual, Rev. 1.6 4-38 Freescale Semiconductor...

  • Page 77: Ber_Enable - Register 30

    TX spectrum. operation until aborted. Continuous RX Mode is useful for looking at current. 0 = Continuous operation disabled; normal operation. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor 4-39...

  • Page 78: Psm_Mode - Register 31

    Operation Bits 15-6, Reserved Bits 5-3 psm_tm[2:0] — Phase shift modulator test mode. psm_tm[2:0] = 0b000 - normal modulated operation. Use only the two stated conditions. psm_tm[2:0] = 0b001 - modulator disabled. MC13192 Reference Manual, Rev. 1.6 4-40 Freescale Semiconductor...

  • Page 79: Serial Peripheral Interface (Spi)

    The following bytes are read or write data. The SPI also supports recursive ‘data burst’ transactions in which additional data transfers can occur. The recursive mode is primarily intended for Packet RAM access and fast configuration of the MC13192. Partial word accesses are not supported.

  • Page 80: Chip Enable (Ce)

    5.2.1.2 SPI Clock (SPICLK) The host drives the SPI Clock (SPICLK) input to the MC13192. Data is clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes state on the trailing (falling) edge of SPICLK.

  • Page 81: Spi Burst Operation

    SPI Singular Transactions Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13192 requires that a complete SPI transaction be framed by CE, and there will be 3 or more bursts per transaction. There are generally two classes of transactions, which are singular and recursive.

  • Page 82: Spi Singular Transaction Signalling

    In this context, a write is data written to the MC13192 and a read is data written to the SPI master. The following SPI bursts will be either the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).

  • Page 83: Symbol / Data Format

    RX Packet RAM Symbol 4 Symbol 3 Symbol 2 Symbol 1 MISO Figure 5-6. RX Symbol Flow Diagram The inverse of the RX symbol / data flow is the case for TX data / symbols. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 84: Spi Recursive Transactions

    SPI overhead and a corresponding increase in programming speed. 1. The primary intent is for the software to be able to rapidly configure the MC13192. 2. Recursive reads and writes are convenient for accessing SPI register values which extend beyond the 16-bit SPI register format.

  • Page 85: Special Case - Packet Ram Access

    5.5.3 Special Case - Packet RAM Access Packet RAM access is a special case access when the MC13192 is used in the Packet Mode. The MC13192 contains three embedded 128-byte ‘Packet RAMs’ used to facilitate reception and transmission of packet data.

  • Page 86: Receive Packet Ram Read Access Error Conditions

    3. Do a recursive SPI read transaction where: a) MCU asserts CE low. b) MCU sends the MC13192 the first SPI burst with header field of R/W bit = 1 and address field Addr[5:0] = 0x01 for the RX_Pkt_RAM register address.

  • Page 87: Transmit Packet Ram Write Access Flow

    3. Do a recursive SPI write transaction where: a) MCU asserts CE low. b) MCU sends the MC13192 the first SPI burst with header field of R/W bit = 0 and address field Addr[5:0] = 0x02 for the TX_Pkt_RAM register address.

  • Page 88: Program Reset (Writing Address 0X00)

    0x00 is written, an internal chip reset of the digital core is generated. All synchronous logic in the MC13192 digital core is reset and the SPI register fields are returned to their default values. This Software Reset has the same effect on the MC13192 digital core as asserting the external RST pin except RAM contents are retained.

  • Page 89: Modes Of Operation

    Transition from the Off to Idle mode occurs when RST is negated to high. Once in Idle mode, the SPI is active and used to control the MC13192. Transition to Hibernate or Doze modes is enabled via the SPI. There are active states of Idle, Transmit (TX), Receive (RX), and Clear Channel Assessment (CCA) modes.
  • Page 90 = et[23:0] HIBERNATE and xcvr_seq = 0x2 set doze_en ATTN = 0 (edge) or tmr_cmp2 = et DOZE Figure 6-2. State Diagram for Packet Mode With Tmr_Cmp2 Enabled States (tmr_trig_en =1) MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...
  • Page 91 = 1 and tc2_prime = et[15:0] ATTN = 0 (edge) or tmr_cmp2 = et DOZE Figure 6-4. State Diagram for Stream Mode With TC2_Prime Enabled State (tmr_trig_en = 1) MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 92: Low Power Modes

    Hibernate is then entered 128 CLKO cycles after hib_en is set. The normal way to exit from Hibernate mode is to assert ATTN which will cause the MC13192 to go to Idle mode. The MC13192 the moves to Idle mode within 20 milliseconds. Asserting RST forces the Off condition.

  • Page 93: Acoma Doze Mode

    Idle or a RST can be used to exit. Acoma mode is entered by setting acoma_en, IRQ_Mask Register 05, Bit 8 = 1. Active Modes There are four active modes for the MC13192 which include, Idle, Transmit (TX), Receive (RX) and Clear Channel Assessment (CCA)/Energy Detect (ED). 6.3.1...

  • Page 94: Controlling Transition To Other Active Modes From Idle

    = 0). However, the RXTXEN signal must also be high for the transition to occur and if the Event Timer is enabled, the transition will be synchronized to the timer compare event. Once Receive or Transmit is entered, the MC13192 will transition back to the Idle mode upon completion of the selected operation. Table 6-2 shows the transceiver sequence field modes.

  • Page 95: Packet Receive Mode

    Receive mode is the state where the transceiver is waiting for an incoming data frame. The advantage of packet receive mode is that it allows the MC13192 to receive the whole packet without intervention from the microcontroller. The entire packet payload is stored in RX Packet RAM and the microcontroller fetches the data after determining the length and validity of the RX packet.

  • Page 96: Aborting A Packet Receive Sequence

    6.3.3.3 Packet Transmit Mode The advantage of packet transmit mode is that it allows the MC13192 to send the whole packet without intervention from the microcontroller. The entire packet payload is pre-loaded in TX Packet RAM, the MC13192 sends the frame, and then the transmit complete status is given to the MCU.

  • Page 97: Stream Mode Data Transfer Tx And Rx Operation

    Event Timer is enabled, the transition will be synchronized to the TC2_Prime compare event. Once Receive or Transmit is entered, the MC13192 will transition back to the Idle mode upon completion of the selected operation.
  • Page 98 •If the timing of the last data transfer on a stream receive is violated, a strm_data_err status will not be issued and the user software must take this into account. These are described in more detail in the following sections. MC13192 Reference Manual, Rev. 1.6 6-10 Freescale Semiconductor...

  • Page 99: Stream Receive Mode

    Stream Receive Mode The advantage of stream receive mode is that it allows the microcontroller to fetch data from the MC13192 as soon as the data arrives. As a result the MCU can begin processing frame information as it arrives and provide a quicker turn-around time if a response is required.

  • Page 100: Aborting A Stream Receive Mode Sequence

    “1” indicates complete status. Also, an interrupt is generated due to the valid status 14. In response of the interrupt request from the MC13192, the microcontroller checks status to clear the interrupt and check the validity of the RX packet.

  • Page 101: Stream Transmit Mode

    Steps 11 and 12 get repeated as required for the payload data. A word must be transferred within 64 µs to keep the packet contiguous. No data transfer is required for the FCS data because it is generated by the onboard transceiver. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor 6-13...

  • Page 102: Clear Channel Assessment (Cca) Modes (Including Link Quality Indication)

    “1” indicate complete status. Also, an interrupt is generated due to the valid status. 14. In response of the interrupt request from the MC13192, the microcontroller checks status to clear the interrupt and check the validity of the TX complete.
  • Page 103 This is not a problem since the purpose of this measurement is to detect a signal above a threshold that is not to exceed -75 dBm. See the 802.15.4 Standard for details. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...
  • Page 104 RX_Pkt_Latch Register 2D, Bits 15 - 8 - reports the average power level b) cca, IRQ_Status Register 24, Bit 1, is set to “1” when a busy channel is detected MC13192 Reference Manual, Rev. 1.6 6-16 Freescale Semiconductor...

  • Page 105: Energy Detect Function (Use_Strm Is Zero)

    IRQ_Status Register 24, Bit 5, is set to “1” to indicate complete status. Also, an interrupt is generated due to the valid status 9. In response of the interrupt request from the MC13192, the microcontroller does the following: a) Determines the busy status of the channel by reading and checking cca_irq and cca b) If required the power level can be determined by reading cca_final[7:0] 10.

  • Page 106: Cca / Ed While In Stream Mode (Use_Strm Is One)

    Frequency of Operation The MC13192 is designed to operate in the 2.4 GHz band, covering 16 channels and using 5 MHz of spacing between each channel. The MC13192 uses two local oscillators (LO). The first LO synthesizer is the main LO for the receiver and the carrier generator for the transmitter.

  • Page 107: Transmit Power Adjustment

    SPI register settings for pa_lvl_course[1:0], PA_Lvl Register 12, Bits 7-6 and pa_lvl_fine[1:0], PA_Lvl Register 12, Bits 5-4. Table 6-3. MC13192 Power Output vs. SPI Settings (Register 12) PA Power Adjust Typical Differential Power at...

  • Page 108: Ghz Pll Out-Of-Lock Interrupt

    IRQ_Status Register 24, Bit 15, is set and any RX or TX operation in progress is automatically terminated. The MC13192 returns immediately to the IDLE state to await interrupt service routine handling. Also, the IRQ is asserted provided the mask bit pll_lock_mask, IRQ_Mask Register 05, Bit 9, is set.

  • Page 109: Timer Information

    Chapter 7 Timer Information Event Timer Block The MC13192 contains an internal Event Timer block that manages system timing. A simplified block diagram is shown in Figure 7-1. et[23:0] tmr_clk 16 MHz Prescale 24-Bit Counter tmr_cmp1[23:0] tmr_prescale[2:0] tc2_prime[15:0] tmr_cmp2[23:0] tmr1_irq...

  • Page 110: Event Timer Time Base

    “Current Time” is defined as the value of the Event Timer internal counter. The current time is programmable, but does not have to be programmed. In the reset condition, the MC13192 current time is set to zero. Current time advances from zero at the tmr_clk clock rate and rolls over to zero after reaching its maximum value.

  • Page 111: Reading Current Time

    “current time” starting at the MSB address. Latching the Timestamp The MC13192 has the ability create a Timestamp or to latch a copy of the “current time” while continuing to increment its internal counter. This timestamp value latched within the Event Timer corresponds to the beginning of a receive packet where the actual payload data begins after the FLI has been received.

  • Page 112: Timer Disable Bits

    If the interrupt mask is set to “1” (enabled), the timer compare status will cause an interrupt and the interrupt signal will stay active until the status bit is cleared via an IRQ_Status read. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 113: Setting Compare Values

    SPI write to the MSB location starts, the comparator is disabled until an SPI write to the LSB location is completed. The preferred procedure for software to change a timer compare value within the MC13192 is to perform a 2-word recursive write of the timer compare field starting at the MSB address.

  • Page 114: Using Tmr_Cmp2[23:0] To Exit Doze Mode

    This allows the host to arm the MC13192 to execute a desired operation at a future time, and go off to perform other necessary system functions.

  • Page 115: Packet Mode Timer_Triggered Tx Or Rx Events

    11. Program the MC13192 for the desired transceiver operation via xcvr_seq[1:0]. 12. Assert the RXTXEN pin and hold high. 13. When “current time” equals tmr_cmp2[23:0], the MC13192 initiates the selected transceiver operation. When tmr2_irq, IRQ_Status Register 24, Bit 2 is set to 1, an external interrupt is generated if the interrupt mask bit (tmr2_mask) was set high.
  • Page 116 12. Program either rx_strm or tx_strm for desired operation. 13. Assert the RXTXEN pin and hold high. 14. When “current time” equals tc2_prime[15:0], the MC13192 initiates the selected transceiver operation. When tmr2_irq, IRQ_Status Register 24, Bit 2 is set to 1, an external interrupt is generated if the interrupt mask bit (tmr2_mask) was set high.

  • Page 117: Interrupt Description

    Chapter 8 Interrupt Description Interrupts Interrupts provide a way for the MC13192 to inform the host microcontroller (MCU) of onboard events without requiring the MCU to constantly query MC13192 status. For a given event, the interrupt flow is as follows.

  • Page 118: Interrupt Sources

    While in Doze mode, a tmr_cmp2 match has Read IRQ_Status Reg occurred and the MC13192 will return to Idle mode. rx_rcvd_irq/ rx_rcvd_mask 1. Rx_rcvd_irq - When in packet data mode, the 1. Read IRQ_Status Reg...

  • Page 119: Output Pin Irq

    Interrupt Description Table 8-1. MC13192 Interrupt Sources (continued) Interrupt Clear Item Status Bit Mask Bit Source Description Mechanism tx_sent_irq/ tx_sent_mask 1. Tx_sent_irq - When in packet data mode, the 1. Read IRQ_Status Reg tx_strm_irq current TX packet in Packet RAM has been completely transmitted, and the transceiver has returned to Idle Mode.

  • Page 120: Pll_Lock_Irq Status Bit And Operation

    Mode” for abnormal behavior if ATTN is asserted to early upon entering Hibernate or Doze mode Interrupts from Exiting Low Power Modes The MC13192 has three low power modes and interrupt generation differs somewhat for each mode. 8.4.1 Exiting Off Mode (Reset) The transceiver is put in reset and stays in reset (Off Mode) through the assertion of RST.

  • Page 121: Exiting Hibernate Mode

    Alternately, Doze has the option of using tmr_cmp2 to exit, except for Acoma Mode which cannot use the timer. When tmr_cmp2 match occurs the doze_irq status will be set. An interrupt request will also occur if doze_mask bit has been enabled. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...
  • Page 122 Interrupt Description MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

  • Page 123: Miscellaneous Functions

    Chapter 9 Miscellaneous Functions Reset Function The MC13192 can be placed in one of two reset conditions either through hardware input RST or by writing to Reset Register 00. 9.1.1 Input Pin RST Asserting input pin RST low places the transceiver in a complete reset condition (Off Mode and power down), and the device stays in this reset mode until RST is released high.

  • Page 124: General Purpose Input/Output

    Miscellaneous Functions General Purpose Input/Output The MC13192 has seven general purpose input/output (GPIO) pins (GPIO1 through GPIO7). Features include: • CMOS logic levels with +/- 1 mA load current • Programmable as inputs or outputs • No programmable pullups are provided •...

  • Page 125: Reading Gpio Input State

    1. GPIO1 becomes an “Out of Idle” indicator (active high) - GPIO1 will always reflect the status of the internal state machine. If the MC13192 is in a TX or RX or CCA/ED sequence, the GPIO1 will be high. Once the sequence ends, the GPIO1 returns to a low state and shows that the transceiver has returned to Idle.

  • Page 126: Crystal Requirements

    9.3.1 Crystal Requirements The MC13192 requires that only a 16 MHz crystal with a <9 pF load capacitance can be used. The load capacitance limitation is required due to internal oscillator circuit and the ability to trim the oscillator as described in the next section.

  • Page 127: Output Clock Pin Clko

    07, Bit 9) Bit clko_doze_en, Control_B register 07, Bit 9, is used to control CLKO during Doze mode. If clko_doze_en is set to 1 before entering Doze mode, CLKO will continue to toggle while the MC13192 is MC13192 Reference Manual, Rev. 1.6...

  • Page 128: Setting Clko Output Drive Strength

    The ATTN assertion low event can also generate an interrupt. The interrupt status bit is attn_irq, IRQ_Status Register 24, Bit 10, and the interrupt mask bit is attn_mask, IRQ_Mask Register 05, Bit 15. MC13192 Reference Manual, Rev. 1.6 Freescale Semiconductor...

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