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• IC Pin Function Description
KEY BOARD IC101 µPD789488GC-A35-8BT (SYSTEM CONTROLLER)
Pin No.
Pin Name
1, 2
CAPH, CAPL
3 to 5
VLC2 to VLC0
6 to 9
COM0 to COM3
10 to 35
S0 to S25
36, 37
P86, P87
38
AVDD
39
VERSION
40 to 46
P66 to P60
47
AVSS
48
VDET2
49
VDET1
50
BEEP
51
PS
52
MOUNT
53
MUTE
P24
54
DATA/EEPROM
55
56
CLK/EEPROM
57
DATA/PLL
58
CLK/PLL
59
CE/PLL
60, 61
P10, P07
62
POWER
LED
63
64
KR3
65 to 67
KR2 to KR0
68
P00
69
IC0
70
XT1
71
XT2
72
VDD
73
VSS
74
X1
75
X2
76
RESET
77
SHIFT
78 to 80
KS2 to KS0
I/O
—
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
—
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
O
Common drive signal output to the liquid crystal display
O
Segment drive signal output to the liquid crystal display
O
Not used
—
Power supply terminal (+2.41V) (for A/D converter)
I
Setting terminal for the destination Fixed at "H" in this set
I
Not used
—
Ground terminal (for A/D converter)
I
Voltage detection signal input terminal "L": 2.1V or less
I
Voltage detection signal input terminal "L": 1.9V or less
O
Beep sound output to the FM/AM front-end
I
Pulse signal input terminal for 1 rotation time measurement
I
Mount state detection signal input terminal "L": mount connected, "H": no connected
O
Radio output muting on/off control signal output terminal "L": muting on
O
Not used
I/O
Two-way data bus with the EEPROM
O
Serial clock signal output to the EEPROM
O
Serial data output to the FM/AM PLL
O
Serial clock signal output to the FM/AM PLL
O
Chip enable signal output to the FM/AM PLL
O
Not used
O
Radio power on/off control signal output terminal "H": power on
O
LED drive signal output of the liquid crystal display back light "L": LED on
I
Key return signal input terminal Not used
I
Key return signal input terminal
O
Not used
—
Connected to the ground
I
Sub system clock input terminal (32.768 kHz)
O
Sub system clock output terminal (32.768 kHz)
—
Power supply terminal (+2.4V)
—
Ground terminal
I
Main system clock input terminal (4.19 MHz)
O
Main system clock output terminal (4.19 MHz)
System reset signal input from the reset signal generator "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
O
Shift clock on/off control signal output terminal "L": shift clock on
O
Key source signal output terminal
Description
ICF-M88B
15
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