Block Diagram - Main Section (2/2) - Sony HW-HD5 Service Manual

5-2. BLOCK DIAGRAM – MAIN Section (2/2) –
IC1003 – IC7001
(Page 18) B
D0 – 15
(Page 18)
C DATA BUS
A1 – 23
(Page 18) D
ADDRESS BUS
(E, Taiwan, Korean, Chinese, Tourist)
D0 – 15
A1 – 20
FLASH MEMORY
XCE 26
IC1102
IC1001_XRE
XOE 28
IC1001_XUWR
XWE 11
R/XB 15
XRST 12
FLASH MEMORY
IC1101
D0 – 15
A1 – 20
XCE 26
XOE 28
XWE 11
R/XB 15
XRST 12
IC3001 – IC7001
E
(Page 18)
NW-HD5
186 191 192
D0 – 15
A1 – 23
(E, Taiwan, Korean, Chinese, Tourist)
187 GAND_XCS1
MAIN SYSTEM CONTROLLER,
X1002
22.5792MHz
137 XTAL
138 EXTAL
IC1001_XCS0
IC1001_XRE
IC1001_XUWR
86 PG0/DAKC0
LEVEL SHIFT
106 RST
Q1001
77 175 151 153
X9501
32kHz
193 182 185 183 184 181 88 89 83
AOUTL 134
AOUTR 133
BEEP
PF4/BEEP 85
HP_MUTE
PR7 163
HP_LINE_SEL
PR6 162
SREQ
PP1/RB 34
WAKEUP
PP0/RP 33
XRESET
D/A CONVERTER PQ6 152
IC1003 (1/2)
DATA_READY
PG1/DREQ0/INT5 87
XINT
PF0/EC0/INT3 81
SS
PC3/SCS0 60
SI
PC2/SI0 59
SO
PC1/SO0 58
SCLK
PC0/SCK0 57
GDAC_PCM0
PI1/ADDT 172
GDAC_LRCK
PI2/LRCK 173
GDAC_BCK
PI3/BCK 174
PE6/SI1 75
PE5/SO1 74
PE4/SCK1 73
PE7/SCS1 76
REAL TIME CLOCK
IC9503
8 OSC OUT SIO 1
SCLK 2
7 OSC IN CE 12
BUFFER
IC9502
19 19
• SIGNAL PATH
: AUDIO
HEADPHONE AMP
IC4301
3 L-IN LOUT 10
1 R-IN ROUT 12
14 BEEP
15 MUTE
16 HP/L
F4301
+2.4V_AD
36 PF2
34 PF0
33 NRST
35 PF1
37 PF3
42 PC3
40 PC1
SUB SYSTEM
CONTROLLER
41 PC2
IC3001
38 PC0
15 P10/PCMD0
14 P12/LRCK0
13 P13/BCK0
12 4 2 1 30 29
X3001
22.5792MHz
MULTI_SIO
NW-HD5
Ver. 1.3
J4301
i /LINE OUT
RM_GND
RM_KEY
RM_TSB
RM_VDD
G (Page 20)