Yamaha DP-U50 Service Manual page 24

DP-U50
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3 7 63 1515 0
IC475 : LC27287B-TF3
Embedded Array
No. Name I/O
1 VSS I
2 XI I
3 XO O
4 /SIOIRQ O
5 /FIFOIRQ O
6 A0 I
7 A1 I
8 A2 I
9 A3 I
10 A4 I
11 A5 I
12 TEST9 I
13 TEST10 I
14 D0 I/O
15 D1 I/O
16 D2 I/O
17 D3 I/O
18 D4 I/O
19 D5 I/O
20 D6 I/O
21 D7 I/O
22 VDD5 I
23 VSS I
24 D8 I/O
TE
L 13942296513
25 D9 I/O
26 D10 I/O
27 D11 I/O
28 D12 I/O
29 D13 I/O
30 D14 I/O
31 D15 I/O
32 RDB I
33 WRL I
34 WRH I
35 GACS I
36 GARST I
37 CPUCLK I
38 DMVDD I
39 USBDACO O
40 CAPTIN I
41 TEST0 I
42 TEST1 I
43 TEST2 I
44 VDD5 I
45 VSS I
46 MCLKAI I
47 MCLKAO O
48 PIO0 I/O
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49 PIO1 I/O
50 PIO2 I/O
51 PIO3 I
52 PIO4 I
.
53 PIO5 I
54 PIO6 I
55 PIO7 I
23
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Function
GND
X'tal in (GND)
X'tal out (OPEN)
Serial IRQ (OPEN)
FIFO IRQ (/EAINT)
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
(OPEN)
(OPEN)
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
+5V
GND
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Read Strobe input
Write Strobe Low input
Write Strobe High input
Bus Chip Select (EACS)
Global Reset input (USBRST)
System clock input
Master Vdd active detection
USB audio data
USB capture audio data in (PAO7)
OPEN
OPEN
OPEN
+5V
GND
X'tal in (11.2896MHz)
X'tal out (11.2896MHz)
Extended I/O port (OPEN)
Extended I/O port (OPEN)
Extended I/O port (OPEN)
x ao
y
YSS928 AC3DATA
YSS928 SURENC
i
YSS928 DIRERR
YSS928 DIRLOCK
YSS928 KARAOKE
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8
No. Name I/O
56 PIO8 I
57 PIO9 I
58 PIO10 I
59 PIO11 I
60 PIO12 I/O
61 PIO13 I
62 PIO14 I/O
63 PIO15 I/O
64 I2CCK O
65 I2SDA I/O
66 VDD5 I
67 VSS I
68 MCLKBI I
69 MCLKBO O
70 TEST3 I
71 TEST4 I
72 TEST5 I
73 TEST6 I
74 TEST7 I
75 TEST8 I
76 PLLCKO I
77 PLLREF O
78 RFCLK I
79 VDD33 I
Q Q
3 6 7 1 3
80 PCH O
81 NCH O
82 DIV2 O
83 VSS I
84 PO O
85 VCNT I
86 R I
87 AVSS I
88 AVDD I
89 VSS I
90 VDD5 I
91 SFS O
92 /S64FS O
93 S128FS O
94 S256FS O
95 SSYNC O
96 R64FS O
97 C64FS O
98 D64FS O
99 S64FS O
100 X64FS O
101 XFS I
102 /X64FS I
103 X128FS I
104 X256FS I
105 XSYNC I
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106 PAI3 I
107 PAI4 I
.
108 PAI5 I
109 PAI6 I
110 VDD33 I
2 9 9 4 2 8
Function
YSS928 OVFB
YSS928 DTSDATA
YSS928 ZEROFLOG
YSS928 CRC
Extended I/O port (OPEN)
YSS928 DBL/V
Extended I/O port (OPEN)
Extended I/O port (OPEN)
I2C serial Bus clock (OPEN)
I2C serial Bus data (OPEN)
+5V
GND
X'tal in (GND)
X'tal out (OPEN)
(OPEN)
(OPEN)
(OPEN)
H: PLL TEST out, L: normal (OPEN)
H: pllclks in, L: NC (OPEN)
H: PLL TEST out, L: normal (OPEN)
PLL clock input
PLL reference clock out
Internal PLL reference clock
+3.3V
1 5 0 5 8 2 9 9 4
PLL PCH out (TEST8: H) (OPEN)
PLL NCH out (TEST8: H) (OPEN)
Internal PLL VCO div2 (OPEN)
GND
Charge pomp out
VCO control input
VCO Bais Registor
GND (for Analog)
+3.3V (for Analog)
GND
+5V
Other device audio clock
Other device audio clock
Other device audio clock (OPEN)
Other device audio clock
Other device audio clock (OPEN)
Render device bit clock (OPEN)
Capture device bit clock (OPEN)
USB bit clock (OPEN)
Other device bit clock (OPEN)
External bit clock (DIR) (OPEN)
External audio clock (DIR)
External audio clock (DIR)
External audio clock (DIR)
m
External audio clock (DIR)
External audio clock (DIR)
co
Patch input (A/D)
Patch input (YSS928 SDOB0)
Patch input (YSS928 SDOB1)
Patch input (YSS928 SDOB2)
+3.3V
9 9
2 8 9 9