Figure 3-9. Dsp Rssi Port - Rx Mode - Motorola ASTRO Digital Spectra Plus Detailed Service Manual

Theory of Operation: ASTRO Spectra VOCON Board
IRQB
DSP56001
U405
SC0
SC1
SC2
SSI
SERIAL
SCK
SRD
STD
NOTE: An asterisk symbol (*) next to a signal name indicates a negative or NOT logic true signal.
ODC is a clock ABACUS II provides to the ADSIC. Most internal ADSIC functions are clocked by this
ODC signal at a rate of 2.4 MHz and is available as soon as power is supplied to the circuitry. This
signal may initially be 2.4 or 4.8 MHz after power-up. It is programmed by the ADSIC through the SBI
signal to 2.4 MHz when the ADSIC is initialized by the MCU through the SPI bus. For any
functionality of the ADSIC to exist, including initial programming, this reference clock must be
present. SBI is a programming data line for the ABACUS II. This line is used to configure the
operation of the ABACUS II and is driven by the ADSIC. The MCU programs many of the ADSIC
operational features through the SPI interface. There are 36 configuration registers in the ADSIC of
which four contain configuration data for the ABACUS II. When these particular registers are
programmed by the MCU, the ADSIC in turn sends this data to the ABACUS II through the SBI.
DIN and DIN* are the data lines on which the I and Q data words are transferred from the ABACUS
II. These signals make up a differentially encoded current loop. Instead of sending TTL type voltage
signals, the data is transferred by flowing current one way or the other through the loop. This helps to
reduce internally generated spurious emissions on the RF board. The ADSIC contains an internal
current loop decoder which translates these signals back to TTL logic and stores the data in internal
registers.
In the fundamental mode of operation, the ADSIC transfers raw baseband data to the DSP. The DSP
can perform IF filtering and discriminator functions on this data to obtain a baseband demodulated
signal. However, the ADSIC contains a digital filter and discriminator function and can provide this
baseband demodulated signal directly to the DSP, this being the typical mode of operation. The
internal digital IF filter is programmable up to 24 taps. These taps are programmed by the MCU
through the SPI interface.
6881076C25-E
8KHz
D8-D23
A0-A2,A13-A15,RD*,WR*
2.4 MHz Receive Data Clock
20 KHz RX Data Interrupt
48KHz TX Data Interrupt
1.2 MHz Tx Data Serial Clock
Serial Receive Data
Serial Transmit Data
Figure 3-9. DSP RSSI Port – RX Mode
IRQB
SDO
ADSIC
U406
SCKR
RFS
SBI
Data In
TFS
DIN
SCKT
Data In*
DIN-
RXD
ODC
TXD
IDC
3-19
Command Board
Interface
J501-40
ABACUS II
Interface
SBI
J501-6
J501-2
J501-1
J501-7
MAEPF-25107-O
September 5, 2008