Sharp LC-32LE240EV Service Manual page 36

Output Interface
LC-32LE240
 Single/dual link 8/10-bit LVDS output
LC-40LE240
 Supports panel resolution up to Full-HD (1920x1080) @ 60Hz
Output Interface
 Supports TH/TI format
 Single/dual link 8/10-bit LVDS output
 Supports dithering options to 6/8-bit output
 Supports panel resolution up to Full-HD (1920x1080) @ 60Hz
 Spread spectrum output for EMI suppression
 Supports TH/TI format
CVBS Video Encoder
 Supports dithering options to 6/8-bit output
 Supports all NTSC/PAL TV Standard
 Spread spectrum output for EMI suppression
 Stand-alone scaling engine
CVBS Video Encoder
 Programmable Hue, Contract, Brightness
 Supports all NTSC/PAL TV Standard
 Supports TTX/CC/WSS output
 Stand-alone scaling engine
CVBS Video Output
 Programmable Hue, Contract, Brightness
 Allows CVBS output of all source inputs
 Supports TTX/CC/WSS output
2D Graphics Engine
CVBS Video Output
 Hardware Graphics Engine for responsive
 Allows CVBS output of all source inputs
 Interactive applications
2D Graphics Engine
 Supports point draw, line draw, rectangle draw/fill, text draw and trapezoid draw
 Hardware Graphics Engine for responsive
 BitBlt, stretch BitBlt, trapezoid BitBlt, mirror BitBlt and rotate BitBlt
 Interactive applications
 Raster Operation (ROP)
 Supports point draw, line draw, rectangle draw/fill, text draw and trapezoid draw
 Support Porter-Duff
 BitBlt, stretch BitBlt, trapezoid BitBlt, mirror BitBlt and rotate BitBlt
VIF Demodulator
 Raster Operation (ROP)
 Compliant with NTSC M/N, PAL B, G/H, I, D/K,
 Support Porter-Duff
 SECAM L/L' standards
VIF Demodulator
 Audio/Video dual-path processor
 Compliant with NTSC M/N, PAL B, G/H, I, D/K,
 Stepped-gain PGA with 25 dB tuning range and 1 dB tuning resolution
 SECAM L/L' standards
 Maximum IF gain of 37 dB
 Audio/Video dual-path processor
 Programmable TOP to accommodate different tuner gain and SAW filter insertion
 Stepped-gain PGA with 25 dB tuning range and 1 dB tuning resolution
loss to
 Maximum IF gain of 37 dB
optimize noise and linearity performance
 Programmable TOP to accommodate different tuner gain and SAW filter insertion
 Multi-standard processing with single SAW
loss to
 Supports silicon tuner low IF output architecture
optimize noise and linearity performance
 Multi-standard processing with single SAW
 Supports silicon tuner low IF output architecture
DVB-T Demodulator
 Digital carrier frequency offset correction: ±500KHz
 Optimised for SFN channels with pre/post-cursive echoes inside/outside the guard
DVB-T Demodulator
 Acquisition range ±857kHz includes up to 3x ±1/6 MHz transmitter offset
 Digital carrier frequency offset correction: ±500KHz
 Meets Nordig Unified 1.0.3, D-Book 5.0, EICTA E-Book/C-Book test requirement
 Optimised for SFN channels with pre/post-cursive echoes inside/outside the guard
 ±400kHz internal carrier offset recovery range
 Acquisition range ±857kHz includes up to 3x ±1/6 MHz transmitter offset
 6.8 usecs echo cancellation at 7 Msym/s
 Meets Nordig Unified 1.0.3, D-Book 5.0, EICTA E-Book/C-Book test requirement
 Supports IF, low-IF, zero-IF inputs
 ±400kHz internal carrier offset recovery range
 Ultra-fast automatic blind UHF/VHF channel scan (constellations and symbol rate)
 6.8 usecs echo cancellation at 7 Msym/s
Connectivity
 Supports IF, low-IF, zero-IF inputs
 Ultra-fast automatic blind UHF/VHF channel scan (constellations and symbol rate)
 Two USB 2.0 host ports
Connectivity
 USB architecture designed for efficient support of external storage devices in
conjunction with
 Two USB 2.0 host ports
off air broadcasting
Miscellaneous
 DRAM interface supporting one 16-bit DDR2 @1066MHz
 Supports PVR
 Supports Common Interface for conditional access support
 Bootable SPI interface with serial flash support
 Parallel interface for external NAND flash support
 Power control module with ultra low power MCU available in standby mode
 380-ball LFBGA package
 Operating Voltages: 1.26V (core), 1.8V (DDR2), 2.5V and 3.3V (I/O and analog)
5.2. MSTAR Block Diagram
36