Table of Contents
Advertisement
TS-3200 User's Manual
Appendix E - Direct Control of the 386EX DIO Pins
The Intel386 EX processor has three 8-bit bi-directional I/O ports, all of which are functionally identical
(Figure 16-1). Each port has three control registers and a status register. All three ports share pins with
internal peripherals. Several of these pins are routed to the DIO ports. If your design does not require a
pin's peripheral function, you can configure that pin for use as an I/O port. For example, if you don't
need IRQ6 for PC/104, you can use the associated pin (386EX P3.4) as a DIO on JP header pin 10.
Each pin can operate either in I/O mode or in peripheral mode. In I/O mode, a pin has three possible
configurations:
•
high-impedance input
•
open-drain output (requires an external pull-up resistor)
•
complementary output
In I/O mode, register bits control the direction (input or output) of each pin and the value of each output
pin. In peripheral mode, the internal peripheral controls the operation (input or output) of the pin.
Each port has three control registers and a status register associated with it (). The control registers
(PnCFG, PnDIR, and PnLTC) can be both read and written. The status register (PnPIN) can only be
read. All four registers reside in I/O address space.
Register
I/O Address
P1CFG
0F820h
P3CFG
0F824h
(read/write)
P1DIR
0F864h
P3DIR
0F874h
(read/write)
P1LTC
0F862h
P3LTC
0F872h
(read/write)
P1PIN
0F860h
P3PIN
0F870h
(read only)
Port n Mode Configuration:
Each bit controls the mode of the associated pin.
0 = Selects I/O mode.
1 = Selects peripheral mode.
Port n Direction:
Each bit controls the direction of a pin that is in I/O mode. If a pin is in
peripheral mode, this value is ignored.
0 = Configures a pin as a complementary output.
1 = Configures a pin as either an input or an open-drain output.
Port n Data Latch:
Each bit contains data to be driven on to an output pin that is in I/O mode.
Write the desired pin state value to this register. If a pin is in peripheral
mode, this value is ignored.
Writing a value to a PL bit causes that value to be driven onto the
corresponding pin.
For a complementary output, write the desired pin value to its PL bit. This
value is actively driven high or low onto the pin.
For an open-drain output, a zero results in an actively driven low on the pin,
a one results in a high-impedance (input) state at the pin.
To configure a pin as an input, write a one to the corresponding PL bit. A one
results in a high-impedance state at the pin, allowing external hardware to
drive it.
Reading this register returns the value in the register – not the actual pin
state.
Port n Pin State:
Each bit of this read-only register reflects the state of the associated pin.
Reading this register returns the current pin state value, regardless of the
pin's mode and direction.
Table 8 – 386EX I/O Port Registers
26
Technologic Systems
Description
05/21/2009
Advertisement
Table of Contents
