Daewoo DVG-8300SE Manual page 69

SCL 24
SDA 23
GCK 7
CK27 9
ACK 25
XIN 2
XOUT 1
RST 6
GOUT1 44
GOUT0 43
VDD 10, 22, 5
VSS 8, 17, 26,
30, 34,
41, 42, 4
VDDA 29, 32,
36.
I Serial bus clock
I/0 Serial bus address and data input and output pin.
Open drain output.
O General Purpose Clock. Clock frequency is determined by the state of
GOUT[1:0] when RST pin is low.
00 : 40.5 MHz clock output.
0 1: 54.0 MHz clock output.
1 0: 67.5 Mhz clock output.
1 1: 81.0 MHz
O 27 MHz clock output pin.
I/O 384*fs Audio clock output pin.
Controlled by CR2[1:0]
0 0: 384 * 44.1 KHz (16.934MHz) clock output.
0 1: 384 * 48.0 KHz (18.432MHz) clock output.
1 0: 384 * 88.2 KHz (33.868MHz) clock output.
1 1. 384 * 96.0 KHz (36.864MHz) clock output.
I 27 Mhz oscillator input
O 27 Mhz oscillator output
I Active low chip reset input. Chip is in the power down mode when the
RST is low.
O Dual function pin.
GCK frequency select pin when RST is low.
General purpose output pin when RST is high
I Dual function pin.
GCK frequency select pin when RST is low.
General purpose output pin when RST is high
+5V Digital power supply.
GND Digital ground
+5V Analog video power supply.
4-11