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IC BLOCK DIAGRAM & DESCRIPTION
IC801 TC90A41AF(DATA
PROCESSOR)
L
'L
_,igital power source OV
I
-lKl
-
Imigital
power
source 5V
i .,- , -xternal Ram data bus
c
I l/n I Eflernal Ram data bus
No.
Name
lfo DESCRIPTION
No.
Name
Vo DESCRIPTION
1
DPCK!
I
Basic
clock input
51
DVR
I
DMO
basic power source
2
DVDD3
-
Digital power source
3.3V
52
DMO
o
Disc Equaliser
output for DVD
3
SVCK1
I
Servo
basic clock input
53
RASN
o
External
RAM
address
selector
4
SVCKO
o
Servo
basic clock
output
54
CASN
o
External RAM address selector
5
DVSS
Digital power source OV
56
MOEN
o
External RAM output Permission signal
6
DVDD3
-
Digital power sourcx23.3V
56
MWEN
o
External RAM readlwrite select
7
N.C
-
N.C
5?
DVSS
-
Digital power source OV
8
H DWT
I
MPU write signal
56
DVDD3
-
Digital power source 3.3V
9
HDRD
I
MPU read signal
59
MA9
o
External RAM address bus
10
HCEN
I
MPU chip selector
e)
MA%
o
Exiemal Ram address bus
11
HDO
I/o MpU data buss
61
MA7
o
Extamal Ram address bus
12
HD!
1/0 MpU data buss
62
MA6
o
External Ram address bus
13
HD2
1/0 MPU data buss
63
MA5
o
External Ram address bus
14
H D3
1/0 MpU data buss
M
MA4
o
External Ram address bus
15
H D4
I/o MpU data buss
65
MA3
o
External Ram address bus
16
HD5
1/0 MplJ data buss
@
MA2
o
External Ram address bus
17
HD6
1/0 MpU data buss
67
MA I
o
External Ram address bus
18
HD7
1/0 MptJ data buss
63
MAO
o
External Ram address bus
19
DVSS
-
Digital power source OV
69
DvS$
-
ni
23
DVDD5
-
Digital power source 5V
70
DVDL~
,
,"
2t
HINT
o
MPU interrupt signal
71
MD7
[
1/0
IF)
22
HAO
I
MpU address buss
72
MD6
,,"
k,
23
HA1
I
MpU address buss
73
MD5
1/0 External Ram data bus
24
PLCK
1/0 Read channel clock Input
74
MD4
1/0 External Ram data bus
25
EDO
-
NC
75
MD3
1/0 External Ram data bus
al
Ku I
N.L
/u
,,, L,
2
1/0 Exlemal Ram data bus
27
ED2
-
N.C
77
MD1
1/0 External Ram data
bus
m
ED3
-
N.C
78
MDO
1/0 External Ram data bus
29
ED4
-
N.C
7?3
SD7
o
MPEG data outpil
3)
ED5
-
N.C
82
SD6
o
MPEG data output
31
ELM
-
N.C
81
SD5
o
MPEG data output
32
ED7
-
N.C
62
SD4
o
MPEG data output
l_C@T 1 ,_...
_.,x..
-
m
n\mc
.
~igltal
power source
OV
Iigital
power
source 5V
.
I _ , ,.IPEG data output
>
1
---
I O IMPEG data output
87
Cni
I fl I htpEG data
Output
.-
,.
.IPEG data output
R
I n l~4PEG data Rehability flag
IPEG output sector synchromse signal
IPEG data effective flag
.
.
..fiPEG data Forwarding clock
;s
-
Digital power source
Q
I
MPEG data request flag
"N
I
Hard reset input
n?
-
~igital power source
'lay status monitor data
'lay status monitor synchronies signal
ieneral purpose PWM output
1-1
,, .,!,
1
,r,la,
uaalu
pv""ul
0""!"-
1
t
----
,
-)igitai power source OV
1
.
,Go,
I
Luw
>UL1ll Iy
""u"
I
1-
3$
PDON
c1 PLL phase error signal output
34
DVDD3
[ - IE
35
PDOP
o
PLL phase error signal output
Er5
SD3
I n Ii,
33
PLLO
o
PLL detection result output
%5
sn7
37
LPFN
I
input f orflL loop
filter
L.
"u,
, _ ,,,
33
LPFO
o
output
for PI-L Imp filter
m
SDO
I ~
IL
33
VCOF
o
VCO
filter output
m
SERI
,
.
r.
40
SLCO
o
Basic
power o utput
for internal
COrTIparatOr
9)
SBGN
o
k
41
AVSS
Analogue power source
91
SENB
o
h
42
AVR
o
/+nalogue power
source for not PLL stem
Q
SDC~
n
h
43
VRC
-
Resister
division point voltage
93
DVS:
44
PVR
o
,4nalogue
power source for PLL stem
w
SRE(
45
AVDD
-
Analogue
power source
%
RSTI
46
BAIS
-
Second basic power OV
%
DVDL.
.
47
RVDD
-
Power source 3.3V
97
STDA
o
F
46
RFIN
1 RF signal input
%
STCK
o
F
49
RVSS
-
Power source OV
93
U PWM
o
c
m
R!lni
-
r,"-+ h-.-;,. ..-(.,-. C-,,.,.0
lca
nvss
-
r
IC903 MC74HC175DR(QUAD
D FLIP-FLOP)
RESET
QO
Qo
DO
D1
m
C!l
GND
Vcc
Q3
53
D3
D2
Fz
Q2
CLOCK
T
Inputs
output
Reset Clock
D
Q
Q
LXXLH
H/HHL
HJLLH
HLX
No Chang(
-76-
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