Sanyo DVD-5100 Service Manual page 68

IC BLOCK DIAGRAM & DESCRIPTION
IC701 TC9461 F(DIGITAL SERVO SIGNAL PROCESSOR)
No.
Name
Vo
DESCRIPTION
No. Name
Vo
DESCRIPTION
1 Vss
-
Digital ground
51 2VREF - Analogue reference power
2 BCK
o Bit clock(l .4122MHz) output
52
SEL o APC circuit otioff signal output
3
AOUT
o
Audio data ouQut 53
FLGA o External flag of internal signal monitor output
4 DOUT o Digital output 54
FLGB o External flag of internal signal monitor output
5 MBOV o Buffer memory over signal output 55
FLGC o External flag of internal signal monitor output
6 IPF
o Correction flag output
%
FKGD o External flag of internal signal monitor output
7 SBOK o CRCC iudoement result of subwde "Q data outout 57
VDD
Diaital mJse Dower source ,- .,.
8
CLCK 1/0 Clock output for subcode "P-"W data read 58
Vss - Digital ground
9 VDD
- Digital power plus source.
59
100 1/0
General purpose 1/0 port
10 Vss
- Digital ground.
a
101
1/0 General purpose IWOport
11 DATA o Sutxade "P-WV
data output,
61
102 Iwo General purpose 1/0 porf
12 SFSY o Frame synchronism signal output by play, &
103 1/0 General purpose 1/0 porl
13 SBSY o Submde
block
synchronism output 63 /DMOUT I Mode setfing for 100,1,2,3
14
SPCK o Clock
output for process status signal read
84
ICKSE I X'tal select
15 SPDA
o
Processor status signal Output. EK IDACT I Test
16 COFS
o
Frame
clock(7,35kHz) output by amendment 85
TESIN
17 MONIT
I Test input
o LSI internal signal monitor 87 TESTIOI
I Test inputioutput
18 VDD -
ninitsl nnwc.r nh
IS sOurw, 68
Vss -
Digital ground
@
Pxl f "DSP clock oscillator inout
-,=..-,~-..-, ~,-.
19
TESIOO
I Test inpufloufput
al P2VRREF
- 2V REF by PLL only
70
Pxo o "DSP clock oscillator output
21 SPDO o VCO sensor frequency shift
71
VDD - Digital pulse power source
22 PDOS
o output of phase error between EFM signal and PLC signal
72
Xvss - Ground for system clock oscillator
a PDO o output of phase error between EFM signal and PLCK signal Z3
xl I System clock oscillator input
24
TMAXS
o TMAX detection result output
74
Xo o System clock oscillator output
z TMAXS o TMAX detection result output 75
XVDD - System clock oscillator pulse power source
2'3 LPFN
I Inversion of
IOW
pass
filter amplifier input
76
DVDD - power source for DIA converter
27 LPFO
o
LOW
pass
filter amplifler output
77
RO o "R" channel data output
28 PVREF
- Dedication of PLL VREF
76
DVSS - DIA mnverter analogue Ground
29 VCOREF
I VCO sensor frequency reference level
79
DVR - DIA converier Reference power source
33 VCOF
o VCO filter F12
LO
o "L
channel data output
31 AVSS
- Analogue ground
81
DVDD - DIA converter powersource
2 SLCO
o
Data slice level generation "DAC" output a
TEST1
I Test porf
23 RFI
I RF signal input
E3
TEST2 I Test pori
34 AVDD
- Analogue power source
M
TEST3 I Test port
3 RFCT
I RFRP signal sensor level input
m BUSO
1/0
Data input for mlcon interface
38 RFZI
1 RFRP zero cross input
85
BUS1
1/0
Data input for micon intertace
37
RFRP I Ripple 67
BUS2 1/0 Data input for mlcon interiace
38
FEI
I Focus error signal input
83
BUS3 Iwo Data input for micon interface
3 SBAD I Subbeam additional signal inpU! 83
VDD - Digital power source
40
TSIN
1 Test input
93
Vss - Digital ground
41 TEI I
Tracking error
i nput 91
BUCK
I Clock input for micon interface
42
TEZI
I Tracking error zero cross inpUt
92
/CCE I Chip enable signal input for micon interface
43 FOO
o Focus equaliser output
S13
TFSTA I T@ct nnti
44 TRO
o Trackmo eaualiser outout
-----
---- ~-,.
94
t
,
= .,-..-.-,..
ITSMOD I Local
test mode
selector
45 I VREF - I
Analnm w rofemnrs camar
95
IRST I Reset signal input
ltrol outout
%
TESTO I Test oori
.,,-, " >-- -,-,-,---
~- ..-,
46
RFGC
o RF magnitude regulation conl ,
1
47 TEBC
o Tracking Blanca control signal output
97
IHSO o Play speed mode flag output
46 FMO
o Field equaliser output
%3
IUHSO o Play speed mode flag output
49 FVO
o
Speed error signal or Field search "EQ" output
SKI
EMPH
o
Subcade "Q' data emphasis flag output
.W DMO
o Disc equaliser output
1(XI
LRCK
o
Channel clock(44,1 kHz) output
IC904 MC74HCOOAF(QUAD 2-INPUT NAND)
-75-
-