Chipset - Asus P5W DH User Manual

4.4.5

Chipset

The Chipset menu allows you to change the advanced chipset settings. Select an
item then press <Enter> to display the sub-menu.
Advanced Chipset Settings
Configure DRAM Timing by SPD
DRAM ECC Mode
Hyper Path 3
DRAM Throttling Threshold
Boot Graphic Adapter Priority
PEG Buffer Length
Link Latency
PEG Root Control
PEG Link Mode
Slot Power
Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according to the
DRAM SPD (Serial Presence Detect). When disabled, you can manually set the
DRAM timing parameters through the DRAM sub-items. The following sub-items
appear when this item is Disabled. Configuration options: [Disabled] [Enabled]
DRAM CAS# Latency [5 Clocks]
Controls the latency between the SDRAM read command and the time the
data actually becomes available. Configuration options: [6 Clocks] [5 Clocks]
[4 Clocks] [3 Clocks]
DRAM RAS# Precharge [4 Clocks]
Controls the idle clocks after issuing a precharge command to the DDR SDRAM.
Configuration options: [2 Clocks] ~ [6 Clocks]
DRAM RAS# to CAS# Delay [4 Clocks]
Controls the latency between the DDR SDRAM active command and the
read/write command. Configuration options: [2 Clocks] ~ [6 Clocks]
DRAM RAS# Activate to Precharge Delay [15 Clocks]
Configuration options: [4 Clocks] ~ [18 Clocks]
DRAM Write Recovery Time [4 Clocks]
Configuration options: [2 Clocks] ~ [6 Clocks]
-2
[Enabled]
[Disabled]
[Auto]
[Auto]
[PCI Express/PCI]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
Enable or Disable
Configure DRAM
Timing by SPD.
Chapter : BIOS setup