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Circuit Operation Description - Sanyo FXR-110GD Service Manual

Compact panel detachable din-size fm-stereo/mw etr cassette receiver with auto-travel/preset tuning
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I
CIRCUIT OPERATION DESCRIPTION
1.
BASIC OPERATION OF PLL FREQUENCY SYNTHESIZER
L
(--– ———––––———– —––____–__
—––—________________,
I
4.5 MHZ
Devider
Voltage
central
oscillator
,
L
w
T
Osc
1/d
'r
Vco
m
fout
[
Low pass
filter
L______________________
1
Programmable
divider
Prescaler
,
L
I
I
P.D.
1/N
lM
or
l/M+l
J
N : Program
control
(FM
only)
I
P!Y.!l
~------ ---------—-
;
I
I
L-_-_---------------------------------_-------_-J
The illustration
above
is a biock diagram
which
is
afunda-
mental
PLL frequency
synthesizer.
In order to obtain
reference
frequency
fr, the frequency
of
4.5 MHZ
generated
from
a crystal
oscillator
(OSC)
is passed
into a divider
circuit
of 1 /d.
This f r is compared
with fr', and runs through
phase detector
(PD)
and low pass filter
(LPF) to be inverted
to direct-current
signal,
which
is then
applied
as varicap
voltage
of voltage
control
oscillator
(VCO),
thereby
controlling
the
oscillation
frequency.
This
oscillation
frequency
fout
is divided
down
to
1/N
by
programmable
divider
(PD), so that one closed loop is fixed in
the relation
of
fout =frxN
therefore,
the operation
of PLL is stabilized.
In case of automatic
channel
selection,
the dividing
ratio N is
altered
by the PD by a command
from controller,
and fout is
changed
accordingly.
Programmable dividar
Since the oscillation
frequency
of VCO
is very high
as com-
pared with fr, it is divided
down
to 1/N (in the case of MW)
to decrease
the difference
from fr in this circuit.
Phasa datactor
This is a circuit to
detect
the difference
in frequency
and phase
between
reference
frequency
fr and comparison
frequency
fr'
in terms of pulses.
Low
pass filter
This circuit is intended to vary and fix the output
voltage
in
order to deliver
a varicap
voltage
necessary
for desired
VCO
frequency,
on the basis of the output
of the phase detector.
Prescaler
The
local
oscillation
frequency
in FM
is higher
than
the
operating
speed of the programmable
divider
of PLL, thereby
opposing
to accurate
operation.
To
avoid
this,
the
local
oscillation
frequency
is preliminarily
divided
down
in this
circuit
to a proper frequency
permitting
reliable
operation
of
the programmable
divider.
Pulse swallow
count
system
is employed.
A couple
of
pro-
grammable
divider
(swallow
counter
and
programmable
counter)
can be selected.
-11
Psc
~-----
----------
—--—
1
1
f
asc
Prescaler
)
.'.-
1
I
l---------------------i
Programmable
divider
(N I <N2)
f OSC={(M+l)NI
+M(N2-NI)}
fr'
=(MN2+NI)
fr'
Prescaler
Swallow
counter
Programmable
counter
I
M+l
t
M
I
N2-N1
The prescaler
at first starts
the frequency
division
with
the
ratio M +1.
Then the swallow
counter
and the programmable
counter
starts
counting
simultaneously.
When
N 1 inputs are
applied,
the swallow
counter
stops
counting.
Then the fre-
quency
division
ratio
of the
prescaler
is switched
to
M.
Programmable
counter
continues
to count
and stops
when
the
input
reaches
N2.
The
frequency
division
ratio
of the
prescaler
switches
back to M + 1 and swallow
counter
and the
programmable
counter
start to count
again.
FM reception
employs
the pulse swallow
count system.
MW
raception
does not employ
the pulse swallow
count
system
but employs
the direct frequency
division
system
and so only
programmable
counter
is operated.
2. GENERAL
DESCRIPTION
OF LOGIC
IC (lC501
)
a) IC801
LC7232-8424
This IC includes
PLL and controller
is a C-MOS
LSI for digital
tuning
of
FM/MW
PLL frequency
synthesizer
system
and
controls
such functions
as FM/MW
automatic
channel
selec-
tions, preset memory
and frequency
digital display driver.
It is
packed
in a 80-pin
flat package.
3. AUTOSTOP
If counter
start, when high level signal is applied to SD terminal
(Q504
base). Then IF frequency
became
10.7MHz
+30kHz
at
FM or 450kHz*3kHz
at MW.
When
SD and IF is agreed
radio
auto search
tuning stops.

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