Sanyo VPC-E7 Service Manual page 37

3. IC905 (H Driver) and IC901 (V Driver)
An H driver (a part of IC905) and V driver (IC901) are neces-
sary in order to generate the clocks (vertical transfer clock,
horizontal transfer clock and electronic shutter clock) which
driver the CCD.
IC905 has clock generating which drives horizontal CCD and
its drives function. These clocks are output from pin (14), (15),
(18) and (19) of IC905. In addition the XV1-XV10 signals which
are output from IC101 are the vertical transfer clocks, and the
XSG1A, XSG1B, XSG2A, XSG2B, XSG2C, XSG3A and
XSG3B signals which are output is superimposed onto XV1,
XV3, XV5, XV7 and XV9 at IC901 in order to generate a ter-
nary pulse. In addition, the XSUB signal which is output from
IC101 is used as the sweep pulse for the electronic shutter,
and the RG signal which is output from pin (21) of IC905 is
the reset gate clock.
Input Buffer
DVD1
C1
AVD1
L2
AVS1
L3
XSUBN
B1
XSG9N
D1
XV2N
D2
XSG7N
E1
XV7N
E2
XSG5N
F1
XV5N
F2
XV3N
G10
XSG3N
F11
XV1N
F10
XSG1N
E11
XV4N
E10
XV9N
D11
XSG10N
K9
XV6N
K11
XSG8N
J11
XV14N
J10
XSG6N
H11
XV13N
H10
XV12N
G2
XSG4N
H1
XV11N
H2
XSG2N
J1
XV8N
J2
XV10N
K1
AVS2
B11
AVD2
C11
DVD2
L10
Fig. 1-3. IC901 Block Diagram
4. IC905 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to
pins (27) of IC905. There are S/H blocks inside IC905 gener-
ated from the XSHP and XSHD pulses, and it is here that
CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier. It is A/C converted internally into
a 12-bit signal, and is then input to IC101 of the CP1 circuit
board. The gain of the AGC amplifier is controlled by pin (31)-
(33) serial signal which is output from IC101 of the CP1 board.
CCDIN
VL2
A4
RG
VH2
A6
H1-H4
VM2
A10
C2 SUB
V2
A2
B4 V7A
V5A
A5
V3A
B6
V1A
A8
V4
B8
V9
A9
V6
C10
B9 V7B
V5B
B7
V3B
A7
B5 V1B
A3 V8
V10
B3
VM1
L4
VH1
L5
VL1
L7
– 4 –
VRB
VRT
VREF
0~18 dB 6~42 dB
CDS PxGA VGA
CLAMP
INTERNAL
CLOCKS
PRECISION
HORIZONTAL
4 TIMING
DRIVERS
CORE
SYNC
AD9949
GENERATOR
HD VD
Fig. 1-4. IC905 Block Diagram
12
12-BIT
DOUT
ADC
HBLK
CLP/PBLK
CLI
INTERNAL
REGISTERS
SL SCK SDATA