K4S641632K (Ic30 : For Avr-1910); Pin Function Description - Denon AVR-1910 Service Manual

K4S641632K (IC30 : for AVR-1910)

PIN FUNCTION DESCRIPTION

Pin
CLK System clock
CS Chip select
CKE Clock enable
A ~ A Address
0 11
BA ~ BA Bank select address
0 1
RAS Row address strobe
CAS Column address strobe
WE Write enable
DQM Data input/output mask
DQ ~ Data input/output
0 N
V /V Power supply/ground
DD SS
V /V Data output power/ground
DDQ SSQ
No connection
N.C/RFU
/reserved for future use
x8
x16
V V 1
DD DD
DQ0 DQ0 2
V V 3
DDQ DDQ
DQ1 N.C 4
DQ2 DQ1 5
V V 6
SSQ SSQ
DQ3 N.C 7
DQ4 DQ2 8
V V 9
DDQ DDQ
DQ5 N.C 10
DQ6 DQ3 11
V V 12
SSQ SSQ
DQ7 N.C 13
V V 14
DD DD
LDQM N.C 15
WE WE 16
CAS CAS 17
RAS RAS 18
CS CS 19
BA0 BA0 20
BA1 BA1 21
A10/AP A10/AP 22
A0 A0 23
A1 A1 24
A2 A2 25
A3 A3 26
V V 27
DD DD
Name
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
Column address : (x8 : CA
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
(x8 : DQ ~
0
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
AVR-1910/1620/1610/790/590
x8
x16
V V
54
SS SS
DQ7 DQ15
53
V V
52
SSQ SSQ
N.C DQ14
51
DQ6 DQ13
50
V V
49
DDQ DDQ
N.C DQ12
48
DQ5 DQ11
47
V V
46
SSQ SSQ
N.C DQ10
45
DQ4 DQ9
44
V V
43
DDQ DDQ
N.C DQ8
42
V V
41
SS SS
N.C/RFU N.C/RFU
40
DQM UDQM
39
CLK CLK
38
CKE CKE
37
N.C N.C
36
A11 A11
35
A9 A9
34
A8 A8
33
A7 A7
32
A6 A6
31
A5 A5
30
A4 A4
29
V V
28
SS SS
Input Function
~ RA ,
0 11
~ CA x16 : CA
0 8 ,
after the clock and masks the output.
SHZ
), (x16 : DQ ~ )
7 0 15
53
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
~ CA )
0 7