LG GX300 Service Manual page 46

3.7.4 Dual Port Memory (CYDMX128B16-65BVXI, U400 )
The CYDMX128B16 consist of an array of 16k, 8k, and 4k words of 16 dual-ported SRAM cells, IO,
address lines, and control signals (CS#, ADV#, OE#, and WE#). Between the two access ports, one is a
dedicated time multiplexed address and data interface; the other is a pin selectable port to either
standard SRAM or time multiplexed address and data interface. Independent control signals for each
port permit simultaneous access to any location in memory. To handle the situation of writing and
reading to the same location, a BUSY# pin is provided on each port. For port to port communication,
an Interrupt (INT#) pin is also available on each port.
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Figure. 3.7.4 Dual Port MEMORY BLOCK DIAGRAM
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3. TECHNICAL BRIEF
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