Lc72723 - JVC UX-V30 Service Manual

LC72723

1.
Pin Assignment
2.
Block diagram
Vdda
REFERENCE
VOLTAGE
Vssa
ANTIALIASING
MPXIN
FILTER
TEST
TEST
3. Pin functions
Pin
Symbol
I/O
No.
Reference voltage output (Vdda/2)
1 O
VREF
Baseband (multiplexed) signal input
MPXIN I
2
Analog power supply (+5V)
Vdda
3
Analog ground
Vssa
4
O Subcarrier input (filter output)
5 FLOUT
Subcarrier input (comparator input)
6 CIN I
Test input
TEST I
7
8 O Crystal oscillator output (4.332MHz)
XOUT
Crystal oscillator input (exeternal reference input)
9 XIN I
Vssd Digtal ground
10
Digtal power supply
11 Vddd
I
Read mode setting (0:master,1:slave)
12 MODE
RDS-ID/RAM reset (positive polarity)
13 RST I
RDS data output
14 RDDA O
RDCL I/O RDS clock output (master mode)/RDS clock input (slave mode)
15
RDS-ID/READY output (negative polarity)
RDS-ID
16
O
READY
VREF
FLOUT CIN
VREF
57kHz
BPF
SMOOTHING
(SCF)
FILTER
CLK(4.332MHz)
OSC
XIN
PLL
(57kHz)
XDUT
Function
UX-V30
CLOCK
Vddd
RECOVERY
(1187.5kHz)
DATA
DECODER
RAM
MDDE
(128-bits)
RDS-ID RDS-ID/
DETECT READY
Vssd
RDDA
RDCL
RST
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