Sharp LC-26GA5F Service Manual page 109

3.3. Description of Pins IC2201
Table 2-1 Signal Descriptions for the Analog Interface Pins
Name Pin
RAIN 37
GAIN 43
BAIN 50
SOGIN 44
FILT 23
HSYNC 65
VSYNC 64
Table 2-2 provides detailed Display/Even Port pin descriptions.
Table 2-2 Display/Even Port Pin Descriptions
Name Pin(s)
DCLK 106
DCLKNEG 107
DVS 101
DHS 102
DEN 103
Type
AI Red/Green/Blue Analog Inputs. These pins receive the Red, Green and
Blue, or YPbPr/YCbCr/YUV analog signals from the analog video source.
AI
For proper operation of the clamp feature, these inputs must be
AI
AC-coupled.
Analog Sync-On-Green or Sync-On-Luma input. Allows recovery of the
HSYNC signal when this pin is AC-coupling to the Green (Red or Blue)
AI
analog signal source. If not used, this pin should be left unconnected.
External PLL Loop Filter. When using the on-chip PLL, this pin must be
AI
connected to an external filter network.
Horizontal Synchronization Input. This digital input signal controls the
DIS horizontal scan frequency by synchronizing the start of the horizontal
scan. The logic polarity of this signal is controlled by the HSPOL bit.
Vertical Synchronization Input. This digital signal controls the vertical scan
DIS
frequency.
Type
DPort Pixel Clock. Output clock for the display port pixel data. DCLK is
enabled by the DCLKEN bit and can be inverted by the DCPOL bit. DCLK
OSR can be set to run at ½ pixel rate, for dual pixel output mode, by setting the
DCK2EN bit. The internal DCLK clock domain can be disabled by the
DCLKOFF bit to reduce power consumption.
DPort Pixel Clock.
OSR
DPort Vertical Sync. DVS can be either active-high or active-low depending
on the VSPOL bit. Width and timing is controlled by the VPLSE and VDLY
OS
registers.
DPort Vertical Sync. DHS can be either active-high or active-low depending
OS
on the HSPOL bit. Sync width can be controlled by the HPLSE register.
DPort Pixel Enable. This signal is active whenever valid data is present.
OS
The polarity is specified by the DENPOL bit.
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Function
Function
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