Deck Cpu Block Diagram - JVC GR-DVA10 Technical Manual

2.7.6 DECK CPU block diagram

J L I P
P C _ I F
P C
D S C _ I F
M E C H A
S E N S O R
D E W
S E N S O R
R O T A R Y
E N C O D E R
I C 5 5 0 1
T G
V . D R V
I C 1 0 0 1
S Y S C O N
C P U
I C 4 3 0 1
C A M E R A
D S P
I C 1 0 0 2
O N
S C R E E N
A _ R E G _ 3 V
C A S _ S W
S Y S C O N E J T _ S W
A _ R E G _ 3 V
R E G
Fig. 2-7-5 DECK CPU block diagram
I C 1 4 0 1 D E C K C P U
PHY_RST 61
72 OSCI PHY_PD 3
PHY_CNA 15
180 MSELECT
89 SYS_CLK
74 SYS_OUT
78 SYS_IN
237 SRV_RDY
55 RESET DV_INT 226
DV_INT 204
1 0 0 O D D _ E V E N
16 VMUTE_IN HID 207
HID_IN 219
FRP 190
TSR 218
TSR 231
SPA 174
77 TXD
DV_RST 99
DV_CS 104
59 RXD OK 37
A D M 0 - 1 5
W E 0 1 2
RE 24
R W S E L 5
AS 47
188 VD
2 8 O S D _ C S
7 5 O S D _ C L K EQ_CS 85
5 8 O S D _ D A T A EQ_RST 120
EQ_TRST 83
ANA_PD 45
29 MIC_CTL
42 MIC_SDA ANA_CS 14
57 MIC_SCL ANA_CLK 109
A N A _ O U T 9 3
184 BCID1 ANA_IN 108
181 BCID2
183 BCID3 V_PB_L 84
135 REC_SAFE
PBH 117
134 REEL_LED REC_I 116
HID_3 119
187 TAPE_LED
199 S_SENS
182 E_SENS
230 S_REEL
189 T_REEL
M D A _ C S 1 9 5
M D A _ C L K 9 1
MDA_IN 94
2 0 0 D E W _ S E N S
D R U M _ P G 1 9 6
D R U M _ F G 2 3 8
148 CAM0 D R U M _ F G 2 2 9
132 CAM1 D R U M _ F G 2 0 1
136 CAM2 D R U M _ R E F 1 9 1
C A P _ F G 1 7 3
CAP_REF 221
C A P _ B R A K E 1
65 D_GAIN
L D _ O N 2 7
2-47
I C 3 1 0 1
1 3 9 4
D V
P H Y
2 4
I C 3 0 0 1
PD0-3
PC0-1
16
10
D E C K _ D S P
16
I C 3 2 0 1
D V _ E Q
V C O A U D
I C 3 3 0 1
D V _ A N A
REG_4.8V
I C 3 5 0 1
P R E / R E C
I C 1 6 0 1
M D A