Pb Equalizer And Atf - JVC GR-DVA10 Technical Manual

2.5.2 PB equalizer and ATF

To:
D V
IC3201
M A I N
P B _ D A T A
V I T E R B I
P B _ C L K
To:
D E C K
C P U
C P U
A D D T
I/F
0:15
In the playback mode the PB ENV signal output from the PB amplifier is branched into two in the IC3301
DV ANA; one is the signal for playback data and the other is that for ATF. The PBO signal output through
the LPF and AGC is sent to the IC3201 DV EQ as that for playback data, while the ATFO signal output
through the BPF and GCA is also sent to the IC3201 DV EQ as that for ATF.
In the IC3201 DV EQ, the playback signal undergoes digitalization (AD1), waveform equalization (AUTO
EQ), SI-NRZI channel decoding (1 + D), and Viterbi-decoding (VITERBI). The resultant signal processed as
mentioned above is output from the IC3201 as the playback data signal. At the same time, the PLL circuit
constructed in this circuitry controls phase correction in order to generate the PB clock synchronizing with
the playback signal. The 41.85MHz signal oscillated by the internal VCO of the IC3301 is output as the PB
clock (PB CLK). Since the internal switch of the IC3301 varies the capacitance of the capacitor, the switch
is turned off to minimize the capacitance of the capacitor when the level of the REC CTL is H, namely, in
the Audio-Dubbing mode. As a result, the response time is shortened in that mode. The discriminator
(DISCRI) compares the 41.85MHz signal oscillated from the VCO with the other 41.85MHz signal
produced from the 81MHz of the main clock in order to detect a difference between the two frequencies. In
the general playback mode, the discriminator outputs a Low-level signal when the frequency difference is
+ 1 % or more or a High-level signal when the difference is − 1 % or more. In the other modes, a Low-level
signal is output when the frequency difference is + 3 % or more or a High-level signal is output when the
difference is − 3 % or more. When the frequency difference is within ± 1 % in the general playback mode or
within ± 3 % in the other modes, the output signal has high impedance. Therefore, a frequency difference, if
there is, is roughly corrected.
Regarding the signal for the ATF, the frequency component of the ATF pilot signal is extracted from the
playback signal by the BPF and the ATF gain is adjusted by the GCA. Then, the ATF circuit in the IC3201
DV EQ detects a tracking difference using the pilot signals of F0, F1 and F2, and data on the detection
result is transmitted to the servo CPU.
D V _ E Q
A U T O
1 + D
E Q
4 1 . 8 5 M H z
A T F A D 2
Fig. 2-5-2 PB equalizer and ATF block diagram
A I N A D 1 P B O
A D 1
P L L
V O A
2 C H
D E T
V O B
D A C
P W M
IC3202
4 1 . 8 5 M H z C L K
D I S C R
D I S C R I
A I N A D 2 A T F O
R E C C L K
2-23
IC3301 D V _ A N A
A G C
P L L E
+
R E F V
-
P L L O
V C O C
C L K O
D T R
P B : H
C T L 1
J I G C O N N R E C C T L
P B _ V C O R E C : H
G C A
A T F _ G A I N
P B _ E N V
L P F
V C O
S W
B P F