Explanation Of Deck Circuit; Deck System Overall Structure - JVC GR-DVA10 Technical Manual

2.5 EXPLANATION OF DECK CIRCUIT

2.5.1 Deck system overall structure

The DVC deck system has such the IC construction as shown in Fig. 2-5-1. The DV-MAIN IC (IC3001)
serves as the center IC of the deck system IC construction, and this system has been incorporated in the
models of the GR-DVX7 and after.
In recording, the deck system processes image data input from the camera section by shuffling and DV
compression and adds parity codes to it as well as the audio data and sub code data input to the deck
system, and saves those data as sync blocks.
The formatter inside the DV-MAIN IC serves as the 24-25 converter for generating ATF pilot signal and the
data column converter for adapting the data to the digital magnetic recording/playback system (scrambled
interleaved NRZI), and it outputs the processed data to the PRE/REC IC as recording data.
In playback the playback signal transmitted from the PRE/REC IC is input to the DV-ANA (IC3301) and
DV-EQ (IC3201) for waveform equalization, and then supplied to the DV-MAIN IC as playback data. The
DV-EQ IC takes charge of various functions such as playback clock generation, VITERBI decoding, ATF
detection, and so on. For details of its functions, refer to the next page.
The DV-MAIN IC processes playback data by the reverse procedure of recording and it transmits playback
data to the camera section and audio section. Since the DV-MAIN IC has the 1394 LINK function, it inputs
and outputs DV data from/to the camera through the 1394 PHY IC (IC3101).
The 16-Mbits DRAM (IC3002) is used as the memory for shuffling/de-shuffling and ECC error correction.
C A M E R A
Compress / De-compress
A U D I O
IC3002
1 6 M D R A M
IC3001
D V _ M A I N
Shuffling / De-shuffling
ECC Encode / Decode
Formatter / Deformatter
1394 LINK
IC3101
1 3 9 4 P H Y
Fig. 2-5-1 DVC deck IC structure
IC3201
IC3301
D V _ E Q
D V _ A N A
Auto EQ
Viterbi
P B V C O
PLL det
D V
IN/OUT
2-22
IC3501
P R E / R E C
A G C
H E A D