Yamaha RX-V459 Service Manual page 48

RX-V459/HTR-5940/DSP-AX459
HTR-5935
IC60 : D70YE101RFP250 (DSP P.C.B)
Decoder/Post Processor
PIN NO. SIGNAL NAME
1 Ground(Vss)
2 AHCLKX0/AHCLKX2
3 AMUTE0
4 AMUTE1
5 AHCLKX1
6 Ground(Vss)
7 ACLKX1
8 Core Supply (CVpp)
9 ACLKR1
10 IO Supply (DVpp)
11 AFSX1
12 AFSR1
13 Ground(Vss)
14 RESET
15 Ground(Vss)
16 Core Supply (CVpp)
17 CLKIN
18 Ground(Vss)
19 TMS
20 Core Supply (CVpp)
21 TRST
22 OSCVss
23 OSCIN
24 OSCOUT
25 OSCVpp
26 Ground(Vss)
27 PLLHV
28 TDI
29 TDO
30 Ground(Vss)
31 IO Supply (DVpp)
32 EMU[0]
33 Core Supply (CVpp)
34 EMU[1]
35 TCK
36 Ground(Vss)
37 EM_CAS
38 EM_WE
39 EM_WE_DQM[0]
40 Ground(Vss)
41 EM_D[7]
42 IO Supply (DVpp)
43 EM_D[6]
44 Core Supply (CVpp)
45 EM_D[5]
46 EM_D[4]
47 Ground(Vss)
48 EM_D[3]
49 EM_D[2]
50 IO Supply (DVpp)
51 EM_D[1]
52 EM_D[0]
53 Core Supply (CVpp)
54 Ground(Vss)
55 EM_D[15]
48
TYPE (1) PULL (2) GPIO (3)
IO - Y McASP0 and McASP2 Transmit Master Clock
IO - Y McASP0 MUTE Output
IO - Y McASP1 MUTE Output
IO - Y McASP1 Transmit Master Clock
IO - Y McASP1 Transmit Bit Clock
IO - Y McASP1Receive Bit Clock
IO - Y McASP1 Transmit Frame Sync (L/R Clock)
IO - Y McASP1Receive Frame Sync (L/R Clock)
IO - N Device reset pin
IO - N Alternate clock input (3.3-V LVCMOS Input)
IO IPU N Test mode Select
IO IPU N Test Reset
PWR - N Oscillator Vss tap point (for filter only)
IO - N 1.2-V Oscillator Input
O - N 1.2-V Oscillator Output
PWR - N Oscillator 1.2-V Vpp tap point (for filter only)
PWR - N PLL 3.3-V Supply Input (requires external filter)
IO IPU N Test Data In
OZ IPU N Test Data Out
IO IPU N Emulation Pin 0
IO IPU N Emulation Pin 1
IO IPU N Test Clock
O - N SDRAM Column Address Strobe
O - N SDRAM Write Enable
O - N Write Enable or Byte Enable for EM_D[7:0]
IO - N EMIF Data Bus [lower 16 Bits]
IO - N EMIF Data Bus [lower 16 Bits]
IO - N EMIF Data Bus [lower 16 Bits]
IO - N EMIF Data Bus [lower 16 Bits]
IO - N EMIF Data Bus [lower 16 Bits]
IO - N EMIF Data Bus [lower 16 Bits]
IO - N EMIF Data Bus [lower 16 Bits]
IO - N EMIF Data Bus [lower 16 Bits]
IO - N EMIF Data Bus [lower 16 Bits]
DESCRIPTION