JVC TH-A5 Service Manual page 23

2.Pin function
Symbol
I/O
Pin No.
SIGO Bottom Envelope Output. Bottom envelope for Mirror detection.
34 MEVO
O
RF signal Input for Mirror. AC coupled inputs for the mirror detection
35
MIN
I
circuit from the pull-in signal output. (PI)
Pull-in Signal Output. The summing signal output of A,B,C,D or PD1,
36 PI
O
PD2 for mirror detection. Reference to VCI.
Defect Output. Pseudo CMOS output. When a defect is detected, the
37
DFT
O
DFT output goes high. Also the servo AGC output can be monitored at
this pin, When CAR bits 7-4 are '0011'.
PI Top Hold pin. An external capacitance is connected between this pin and VPB.
38 TPH
-
SIGO Bottom Envelope pin. An external capacitance is connected
39 MEV
-
between this pin and VPB.
Mirror Envelope Input. The SIGO envelope input pin.
40 MEI
I
Tracking Error Signal Output. Tracking error output reference to VCI.
41
TE
O
Focusing Error Signal Output. Focus error output reference to VCI.
42
FE
O
Center Error Signal Output. Center error out put reference to VCI.
43 CE
O
Center Error LPF pin. An external capacitance is connected between
44
LCN
-
this pin and the LCP pin.
Center Error LPF pin. An external capacitance is connected between
45 LCP
-
this pin and the LCN pin.
Serial Clock. Serial Clock CMOS input. The clock applied to this pin
46
SCLK
I
is synchronized with the data applied to SDATA. (Not to be left open).
Serial Data. Serial data bi-directional CMOS pin. NRZ programming
47
SDATA
I/O
data for the internal registers is applied to this input. (Not to be left open)
Serial Data Enable. Serial enable CMOS input. A high level input
48 SDEN
I
enables the serial port. (Not to be left open)
Hold Control. ATTL compatible control pin which, when pulled high, disables the RF AFC
49 HOLD1
I
charge pump and holds the RE AGC amplifier gain at its present value. (open high)
Ground. Ground pin for the RF block and serial port.
50
VNA
-
Differential Normal Output. Filter normal outputs.
51 FNN
O
Differential Normal Output. Filter normal outputs.
52
FNP
O
Analog inputs for RF Single Buffer. Differential analog inputs to the RF single-ended
53
DIP
I
output buffer and full wave rectifier.
Analog inputs for RF Single Buffer. Differential analog inputs to the RF single-ended
54
DIN
I
output buffer and full wave rectifier.
Reference Resistor Input. An external 8.2 kohm, 1% resistor is
55 RX
-
connected from this pin to ground to establish a precise PTAT
(proportional to absolute temperature) reference current for the filter.
The RF AGC integration capacitor CBYP, is connected between BYP and VPA.
56
BYP
I/O
Single Ended Normal Output. SIngle-ended RF output.
57
SIGO
O
Power. Power supply pin for the RF block and serial port.
58 VPA
-
AGC Amplifier Inputs. Differential AGC amplifier input pins.
59
AIP
I
AGC Amplifier Inputs. Differential AGC amplifier input pins.
60
AIN
I
Differential Attenuator Output. Attenuator outputs.
61 ATON
O
Differential Attenuator Output. Attenuator outputs.
62
ATOP
O
RF Signal Input. Single-ended RF signal attenuator input pin.
63 CDRF
I
CD RF Signal Output. Single ended CD RF summing output.
64 CDRFDC
O
Function
TH-A5
(2/2)
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